Semiconductor memory device suitable for mounting on...

Static information storage and retrieval – Read/write circuit – Data refresh

Reexamination Certificate

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C365S149000, C365S189030

Reexamination Certificate

active

07983103

ABSTRACT:
A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.

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Notice of Grounds of Rejection mailed Mar. 16, 2010 in a corresponding Japanese patent application and an English-language translation, 9 pages.
Taiwanese Office Action and Search Report dated Jan. 25, 2011 in a corresponding application, and an English-language translation, 9 pages.

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