Semiconductor memory device suitable for high integration

Static information storage and retrieval – Systems using particular element – Semiconductive

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365210, 365200, G11C 1300

Patent

active

054485169

ABSTRACT:
A chip is divided into at least four regions of two rows and two columns. In each region, memory array blocks are provided between corresponding first control circuits disposed in the column direction at a constant pitch. A column decoder is disposed adjacent to the first control circuit. Second control circuits are disposed corresponding to the first control circuits. The second control circuits excluding the second control circuit on the column decoder side are formed in the same pattern.

REFERENCES:
patent: 5210597 (1993-05-01), Kakiuchi et al.

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