Semiconductor memory device, semiconductor device, and...

Details Semiconductor memory device, semiconductor device, and... Semiconductor memory device, semiconductor device, and...

1999-09-28

2001-01-23

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S149000

Reexamination Certificate

active

06178121

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor memory device such as a DRAM (dynamic random access memory), a semiconductor device, and an electronic instrument using the semiconductor device, and more particularly to control of the potential of the cell plate of a memory cell transistor.
BACKGROUND ART
FIG. 6
shows a memory cell array of a conventional DRAM. In
FIG. 6
, memory cells
1
-
4
are provided with N-type MOS transistors (hereinafter called “NMOS transistor”)
5
,
8
,
10
, and
12
and data-storing capacitors
7
,
9
,
11
, and
13
, respectively. Bit lines
36
and
37
and word lines
38
-
41
are connected to the memory cells
1
-
4
. A potential VCC/2 which is the half the power potential VCC is applied to a cell plate electrode
14
. A sense amplifier circuit
21
comprises P-type MOS transistors (hereinafter called “PMOS transistor”)
22
-
24
and NMOS transistors
25
-
27
. A precharge circuit
32
includes PMOS transistors
33
-
35
. Data to be written in the memory cells
1
-
4
is input to a data-input circuit
30
A, and the data read out from the memory cells
1
-
4
is amplified by the sense amplifier
21
to be output from a data-output circuit
30
B.
FIG. 7
is a timing chart showing an operation of writing data in the memory cell
1
of the DRAM shown in
FIG. 6. A
signal SPR is grounded to precharge the bit lines
36
and
37
with the potential of VCC/2 before data is written in the memory cell
1
. The potential of the word line
38
is changed from the ground potential GND to a high potential VPP to turn on the transistor
5
.
At this time, the potential of the bit line
36
changes corresponding to the charge stored in the data-storing capacitor
7
. Specifically, when the data “HIGH” has been written in the memory cell
1
, the potential of the bit line
36
changes to a potential that is &Dgr;V1 lower than the precharge potential VCC/2 as shown by the solid line in FIG.
7
. As a result, the potential of a node
6
changes to a potential that is &Dgr;V2 lower than the potential VCC/2 as shown by the broken line in FIG.
7
. When the data “LOW” has been written in the memory cell
1
, the potential of the bit line
36
changes to a potential that is &Dgr;V1 higher than the precharge potential VCC/2 as shown by the broken line in FIG.
7
. This results in the potential of the node
6
changing to a potential that is &Dgr;V2 higher than the potential VCC/2 as shown by the solid line in FIG.
7
.
The data-input circuit
30
sets the potential of the bit line
36
at the power potential VCC (or ground potential GND) in response to the data-input signal. In this case, the bit line
37
is at the ground potential GND (or power potential VCC). When the potential of the bit line
36
is set at the power potential VCC, a charge with the power potential VCC (the node
6
is at VCC) is stored in the data-storing capacitor
7
. Therefore, the data “HIGH” is written in the memory cell
1
. When the potential of the bit line
36
is set at the ground potential GND, a charge with the ground potential GND (the node
6
is at GND) is stored in the data-storing capacitor
7
. Therefore, the data “LOW” is written in the memory cell
1
.
Since each of the word lines
39
-
41
in the memory cell transistors
2
-
4
is at the ground potential GND, no writing operation is performed if the transistors
8
,
10
, and
12
are turned off.
FIG. 8
is a timing chart showing an operation of reading out data from the memory cell
1
of the DRAM shown in FIG.
6
. In the data-readout operation shown in
FIG. 8
, only points differing from the data-writing operation shown in
FIG. 7
will be described.
In the readout operation shown in
FIG. 8
, after the potential of the word line
38
is raised from the ground potential GND to a high potential VPP, the potential of a signal SSA is raised from the ground potential GND to the power potential VCC. At this time, the sense amplifier
21
amplifies the potential of the bit line
36
up to the power potential VCC (or ground potential GND) to read out data. In this case, the potential of the bit line
37
is amplified up to the ground potential GND (or power potential VCC). At the same time, the potential of the node
6
returns to the power potential VCC (or ground potential GND) to conduct a refresh operation.
In the memory cells
2
-
4
, no data-readout operation is performed if each of the word lines
39
-
41
is at the ground potential GND and the transistors
8
,
10
, and
12
are turned off.
In this prior art, a cell plate electrode
14
is at a constant potential as high as VCC/2 and the node
6
is at the power potential VCC or at the ground potential GND after writing and readout operations. Therefore, variation in the potential of the bit line
36
is small, both in a readout operation after a write-operation and in a continuous readout operation.
A variation &Dgr;V1 in the potential of the bit line
36
is represented by the following equation (1) or (2) on the premise that the capacitance of the memory cell
1
is Cmc and the load on the bit line
36
is Cbl.
&Dgr;V1=f(Cmc, Cbl)×(VCC−Vcc/2)  (1)
&Dgr;V1=f(Cmc, Cbl)×(GND−Vcc/2)  (2)
The function f(Cmc, Cbl) in the above equation (1) is given by the following equation (3).
f(Cmc, Cbl)=1/[1+(Cbl/Cmc)]  (3)
The load capacitance Cbl on the bit line
36
increases with an increase in the number of memory cells connected to the bit line
36
. In this case, the potential variation &Dgr;V1 of the bit line
36
decreases from the equations (1)-(3). In order to avoid this phenomenon, measures may be taken in which the bit line
36
is divided in the longitudinal direction of
FIG. 6
to shorten the length per line. However, the number of sense amplifiers
21
increases in proportion to the number of divided bit lines, thereby increasing the area of a semiconductor memory device in a semiconductor device.
Such a small potential variation &Dgr;V1 of the bit line
36
causes unstable performance of the sense amplifier
21
due to noises and the like. This also hinders high speed access to a memory because of a time-consuming operation of the sense amplifier
21
. Moreover, if the power voltage is made lower using prior art technology to reduce power dissipation, the potential variation &Dgr;V1 of the bit line is further decreased, whereby it is impossible to perform an operation at low voltages.
An object of the present invention is to provide a semiconductor memory device which is improved in the noise immunity of a sense amplifier and can attain high speed performance of a sense amplifier, a semiconductor device, and an electronic instrument using the same.
A further object of the present invention is to provide a semiconductor memory device which can reduce power dissipation, a semiconductor device, an electronic instrument using the same.
DISCLOSURE OF THE INVENTION
A semiconductor memory device according to the present invention comprises:
a plurality of word lines;
a plurality of bit line pairs;
a plurality of memory cells, each of the memory cells being connected to one of the word lines and also to one of the bit line pairs;
a plurality of potential-control circuits; and
a plurality of sense amplifiers which amplify data read-out from the plurality of memory cells through the plurality of bit line pairs to output the amplified data;
wherein each of the memory cells comprises:
a transistor comprising a control electrode and two input/output electrodes, the control electrode being connected to one of the word lines, and one of the input/output electrodes being connected to a bit line of one of the bit line pairs; and
a data-storing capacitor comprising first and second electrodes, the first electrode being connected to the other of the input/output electrodes of the transistor, and the second electrode being connected to one of the potential control circuits;
wherein each of the plurality of potential control circuits changes the potential of the second electrode

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