Semiconductor memory device, rewrite processing method...

Static information storage and retrieval – Read/write circuit – Common read and write circuit

Reexamination Certificate

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C365S189160, C365S189070

Reexamination Certificate

active

07633816

ABSTRACT:
A comparing unit (12) in a readout control unit (11) compares one bit data stored in a memory body (20) with a value stored in a data storage unit B[m] which is prepared to store the one bit data. The data storage unit B[m] includes three memory cells MC[k] and the stored value of the data storage unit B[m] is obtained by a logical operation unit (16) operable to calculate an exclusive OR with respect to the three memory cells MC[k]. When mismatching is detected in the comparing unit (12), a rewrite cell determination unit (13) determines one of the three memory cells MC[k], to which rewriting of the stored value is performed. In the case where the stored value in the data storage unit B[m], if the data storage unit B[m] has a memory cell MC[k] to which writing can be performed, the writing is performed in priority to erasing.

REFERENCES:
patent: 6421279 (2002-07-01), Tobita et al.
patent: 53-087636 (1978-08-01), None
patent: 04-289599 (1992-10-01), None
patent: 2002-366420 (2002-12-01), None
patent: 2003-324150 (2003-11-01), None

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