Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-11-21
2004-11-02
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S233100
Reexamination Certificate
active
06813210
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device requiring refresh operation.
2. Description of the Background Art
Recent reduction in size and power consumption of electronic equipments causes strict requirement for reduced power consumption of the semiconductor memory devices to be mounted to such electronic equipments. A DRAM (Dynamic Random Access Memory), one of a representative example of semiconductor memory devices, requires refresh operation for holding storage data. Therefore, power consumption can be significantly reduced by conducting refresh operation with an appropriate cycle.
In order to hold the storage data of the DRAM, the DRAM conducts refresh operation by reading, amplifying and rewriting the data in a periodic manner in each memory cell to be refreshed. In general, in the refresh operation, every memory cell connected to the word line selected by a row address is refreshed simultaneously.
The conventional DRAM has a self-refresh mode, a mode for holding storage data, as a stand-by mode corresponding to a battery backup period and the like. In the self-refresh mode, the DRAM automatically generates a row address and automatically selects a word line for refresh operation. The DRAM conducts refresh operation in refresh cycle according to a refresh signal that is periodically generated by an internal refresh timer.
The refresh cycle for refresh operation is determined by the time period for which the memory cells can hold the data, that is, the data holding time. The data holding time is dependent on a leak current of the memory cell. In a memory cell that is sensitive to temperature change, the leak current becomes less than three orders higher as the temperature increases by 100° C. Therefore, the refresh cycle must be appropriately determined according to the temperature.
The conventional DRAM cannot appropriately regulate the refresh cycle of the self-refresh operation according to temperature change. In order to ensure that the memory cells hold the storage data at high temperature, the conventional DRAM determines the refresh cycle according to the capability of the DRAM at high temperature. Therefore, the refresh operation is conducted unnecessarily frequently at low temperature, thereby unnecessarily increasing power consumption of the refresh operation. Even for a DRAM having temperature-dependent circuitry, it is difficult to internally regulate the refresh cycle to a desired cycle at both high temperature and low temperature. Note that “high temperature” generally refers to a temperature in the range of 70 to 80° C. or higher, and “low temperature” refers to room temperature or a temperature below room temperature.
As described above, the refresh cycle of the self-refresh operation must be appropriately determined so as to ensure that the memory cells hold the storage data and to prevent excessive power consumption. Therefore, a regulator regulates the refresh cycle of the self-refresh operation according to the capability of the semiconductor memory device. In order to regulate the refresh cycle, it is necessary to measure the refresh cycle.
However, it is difficult for the conventional DRAM to measure the refresh cycle even if it has circuitry for measuring the refresh cycle in the self-refresh operation. For example, this is because the refresh cycle must be measured with a waveform measuring device such as oscilloscope being connected to a terminal that is not used normally, or because there is no appropriate waveform measuring device, or connection of the waveform measuring device is troublesome.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device for varying a refresh cycle according to a temperature change and conducting refresh operation with an appropriate refresh cycle.
It is another object of the present invention to provide a semiconductor memory device capable of easily measuring a refresh cycle of self-refresh operation.
According to a first aspect of the present invention, a semiconductor memory device includes a memory cell array including a plurality of memory cells arranged in a matrix, and a refresh control circuit periodically executing refresh operation in order to hold information stored in the plurality of memory cells. The refresh control circuit includes a refresh timer determining a refresh cycle and generating a refresh signal in the refresh cycle, and a refresh address generator sequentially generating, in response to the refresh signal, a refresh row address designating a row of memory cells to be subjected to the refresh operation. The refresh timer includes a voltage regulator regulating an output voltage according to reduction in temperature by using a differential amplifier, an oscillator receiving the output voltage from the voltage regulator and generating an internal signal whose generation cycle is increased with reduction in the output voltage, and a refresh signal generator generating the refresh signal based on the internal signal.
In the first aspect of the present invention, the voltage regulator is formed from the differential amplifier that operates according to a temperature change, and the refresh timer increases the refresh cycle with reduction in temperature based on the output voltage from the voltage regulator.
Accordingly, the above semiconductor memory device executes refresh operation with an appropriate, stable refresh cycle from high temperature to low temperature, thereby enabling reduction in power consumption required for refresh operation.
Preferably, the voltage regulator outputs a constant output voltage when a temperature is less than a prescribed value.
Preferably, the voltage regulator includes a first constant current circuit, a second constant current circuit, a temperature correction circuit, and a bias voltage output circuit. The first constant current circuit outputs a first voltage based on a resistance value of a first resistor having first temperature characteristics. The second constant current circuit outputs a second voltage based on a resistance value of a second resistor having positive second temperature characteristics that have a temperature gradient greater than that of the first resistor. The temperature correction circuit compares the second voltage with the first voltage, and outputs a third voltage having positive temperature characteristics based on the comparison result. The bias voltage output circuit converts the third voltage for a match to temperature characteristics of the refresh cycle, and outputs the output voltage.
According to a second aspect of the present invention, a semiconductor memory device includes a memory cell array including a plurality of memory cells arranged in a matrix, a refresh control circuit periodically executing refresh operation in order to hold information stored in the plurality of memory cells, a measuring circuit generating a measurement signal in response to a first command applied to the semiconductor memory device in a refresh cycle measuring mode, and an output circuit for outputting the measurement signal to outside. The refresh control circuit includes a refresh timer determining a refresh cycle and generating a refresh signal in the refresh cycle, and a refresh address generator sequentially generating, in response to the refresh signal, a refresh row address designating a row of memory cells to be subjected to the refresh operation. The refresh timer starts counting operation for generating the refresh signal in response to a second command applied to the semiconductor memory device in the refresh cycle measuring mode. The measuring circuit receives the refresh signal that is generated by the refresh timer after the refresh cycle based on the second command. The measuring circuit outputs the measurement signal having a first logic level to the output circuit when the measuring circuit receives the refresh s
Ichiguchi Tetsuichiro
Matsumoto Junko
Nagasawa Tsutomu
Okamoto Takeo
Suwa Makoto
McDermott & Will & Emery
Renesas Technology Corp.
Tran M.
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