Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2003-02-21
2004-04-06
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S233100, C365S230030
Reexamination Certificate
active
06717879
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device capable of reading at high speed.
2. Description of the Background Art
A semiconductor memory device used mainly in a recent computer, such as a synchronous dynamic random access memory (SDRAM), performs a read operation with a combination of an activate command (ACT command) activating a word line and a read command (RD command) reading a value stored in a sense amplifier. Performing a burst operation outputting data at plural column addresses continuously, SDRAM can outputs data without a pause even if RD commands for the same word line are continuously inputted.
In a case where a read/write operation is performed on a memory cell connected to another word line, however, it is required that after a word line activated currently is deactivated, an objective word line is activated. Since a time is necessary for the operation, read-out data is interrupted somewhere in the course, thereby reducing an effective value of a transfer rate.
In SDRAM, in order to prevent reduction in a transfer rate, a memory region is divided into sections called memory banks each capable of operating independently. In a case where accesses are performed to memory cells at plural row addresses in the same memory bank, however, the effect of division of a memory region into memory banks has not been able to be obtained.
FIG. 21
is a circuit diagram showing a configuration in the neighborhood of a sense amplifier band of a prior art SDRAM.
Referring to
FIG. 21
, there are placed memory cell arrays MA#
00
and MA#
11
sharing a sense amplifier band SABX on both sides thereof in which plural sense amplifiers are disposed like a band. Memory cell array MA#
00
includes plural memory cells Cell
00
, Cell
10
, Cell
01
and Cell
11
, . . . arranged in a matrix. Each memory cell includes: a capacitor
16
whose one end is fixed to a self-plate potential Vcp at a constant potential; and a transistor
18
, connected between a corresponding bit line and the other end of capacitor
16
, and having a gate connected to a corresponding word line.
Sense amplifier band SABX includes: a sense amplifier
962
; an equalize circuit
922
; and a connection circuit
964
, all corresponding to a bit line pair BL
0
and /BL
0
. Sense amplifier band SABX further includes: a sense amplifier
963
; an equalize circuit
923
; and a connection circuit
965
, all corresponding to a bit line pair BL
1
and /BL
1
.
Sense amplifier band SABX further includes: an isolation gate
960
, becoming conductive in response to activation of a signal BLTG
0
to connect bit line pair BL
0
and /BL
0
to equalize circuit
922
and sense amplifier
962
, while isolating sense amplifier
962
and equalize circuit
922
from bit line pair BL
0
and /BL
0
in response to deactivation of signal BLTG
0
; and an isolation gate
961
, connecting bit line pair BL
1
and /BL
1
to sense amplifier
963
and equalize circuit
923
in response to activation of signal BLTG
0
, while isolating sense amplifier
963
and equalize circuit
923
from bit line pair BL
1
and /BL
1
in response to deactivation of signal BLTG
0
.
Note that sense amplifier
962
and equalize circuit
922
are also used by bit line pair BL
10
and /BL
10
included in memory cell array MA#
11
.
For this reason, sense amplifier band SABX further includes: an isolation gate
966
, connecting bit line pair BL
10
and /BL
10
to sense amplifier
962
and equalize circuit
922
in response to activation of a signal BLTG
1
, while isolating sense amplifier
962
and equalize circuit
922
from bit line pair BL
10
and /BL
10
in response to deactivation of signal BLTG
1
; and an isolation gate
967
, connecting bit line pair BL
11
and /BL
11
to sense amplifier
963
and equalize circuit
923
in response to activation of signal BLTG
1
, while isolating sense amplifier
963
and equalize circuit
923
from bit line pair BL
11
and /BL
11
in response to deactivation of signal BLTG
1
.
In order to reduce a layout area for sense amplifiers, there has been generally well used a shared sense amplifier configuration in which two bit line pairs are disposed on both sides of a sense amplifier.
A sense amplifier is controlled by drive signals S
0
and /S
0
. Since signals S
0
and /S
0
perform an independent operation in each block, they are differentiated from those for other blocks by attaching each block number thereto. Therefore, for example, a drive signal corresponding to block BLOCK
0
is indicated with S
0
and a drive signal corresponding to block BLOCK
1
is indicated with S
1
.
Equalize circuits
922
and
923
each include: a transistor being connected to a complementary bit line pair in response to a signal BLEQ and two transistors, being conductive in response to signal BLEQ to couple two bit lines constituting a bit line pair to a potential VBL.
Connection circuits
964
and
965
connect corresponding bit lines to local IO lines LIO and /LIO in response to activation of respective column select lines CSL
0
and CSL
1
.
Data read-out onto local IO lines LIO and /LIO are transmitted onto global IO lines GIO and /GIO through a connection circuit
968
becoming conductive in response to signal IOSW
0
and given to an input/output circuit
14
.
FIG. 22
is a circuit diagram showing a configuration of a sense amplifier control circuit
1005
generating internal signals mainly used in control of a sense amplifier band of a prior art SDRAM.
Referring to
FIG. 22
, a control circuit
1002
receives a command CMD and an address ADDRESS, and, in a case where activate command ACT and a precharge command PRE as commands are given externally, when address ADDRESS corresponding to memory block BLOCK
0
is inputted, outputs signals ACT
0
and PRE
0
generated in response to the inputs.
Here, since memory block BLOCK
0
is handled as a representative, there will be shown only a configuration associated with signal B
0
SEL selecting memory block BLCK
0
below. For convenience in description, inputted commands are all directed to bank
0
as an object.
Sense amplifier control circuit
1005
includes: a gate circuit
1038
detecting that signal ACT
0
is at H level and row addresses RA
5
and RA
6
are both at L level to activate an output thereof to L level; an inverter
1040
receiving an output of gate circuit
1038
; and an SR latch circuit
1042
, being set in response to an output of inverter
1040
, and being reset in response to signal PRE
0
. Signal B
0
SEL indicating selection of memory block BLOCK
0
is outputted from the Q output of SR latch circuit
1042
.
Sense amplifier control circuit
1005
further includes: a gate circuit
1012
activating an output thereof to L level when signals B
0
SEL and ACT
0
are both at H level and signal RA
4
is at L level; an inverter
1014
receiving an output of gate circuit
1012
to invert; a delay circuit
1028
receiving signal PRE
0
to delay; and an SR latch circuit
1016
, being set in response to an output of delay circuit
1028
, and being reset in response to an output of inverter
1014
to output signal BLTG
1
from the Q output thereof.
Sense amplifier control circuit
1005
further includes: a NAND circuit
1018
receiving signals RA
4
, B
0
SEL and ACT
0
; an inverter
1020
receiving an output of NAND circuit
1018
to invert; an SR latch circuit
1022
, being set in response to an output of delay circuit
1028
, and being reset in response to an output of inverter
1020
to output signal BLTG
0
from the Q output thereof; and an SR latch circuit
1024
, being set in response to an output of delay circuit
1028
, and being reset in response to signal ACT
0
to output equalize signal BLEQ.
Sense amplifier control circuit
1005
further includes: a delay circuit
1026
receiving signal ACT
0
; a delay circuit
1030
receiving an output of delay circuit
1026
; a NAND circuit
1032
receiving an output of delay circuit
1030
and signal B
0
SEL; an inverter
1034
receiving an output of NAND circuit
1032
to
Auduong Gene
McDermott & Will & Emery
Renesas Technology Corp.
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