Semiconductor memory device requiring performance of...

Details Semiconductor memory device requiring performance of... Semiconductor memory device requiring performance of...

1999-07-26

2002-07-02

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

06415399

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for testing a semiconductor device, and more particularly to a semiconductor memory device requiring performance of a plurality of tests for each of plurality of memory circuits and a method for testing the same.
2. Description of the Background Art
FIG. 4
is a block diagram showing a structure of a synchronous dynamic random access memory (hereinafter referred to as SDRAM)
30
connected to a tester
20
. First, SDRAM
30
will be described.
With reference to
FIG. 4
, SDRAM
30
includes a control signal generation circuit
31
, a command decoder
32
, an address buffer
33
, a clock buffer
34
, memory arrays
35
a
-
35
d,
row decoders (RD)
36
a
-
36
d,
column decoders (CD)
37
a
-
37
d,
sense amplifiers+input/output control circuits
38
a
-
38
d
and a data input/output circuit
39
.
Control signal generation circuit
31
receives a variety of control signals such as /RAS, /CAS and /WE supplied from an external source and generates and supplies a variety of internal control signals to command decoder
32
. Command decoder
32
decodes these internal control signals, generates a variety of command signals CMD
0
-CMDi (where i is an integer equal to or larger than 0) and controls SDRAM
30
as a whole by these command signals CMD
0
-CMDi.
Address buffer
33
takes in address signals A
0
-Aj (where j is an integer equal to or larger than 0) supplied from an external source as row address signals X
0
-Xj or column address signals Y
0
-Yj, and supplies row address signals X
0
-Xj and column address signals Y
0
-Yj to row decoders
36
a
-
36
d
and column decoder
37
a
-
37
d,
respectively. Clock buffer
34
receives a clock signal CLK supplied from an external source, generates and supplies to SDRAM
30
as a whole an internal clock signal CLK′. SDRAM
30
operates in synchronization with internal clock signal CLK′.
Memory arrays
35
a
-
35
d
constitute banks #
0
-#
3
, respectively. Each of memory arrays
35
a
-
35
d
is arranged as a matrix and includes a plurality of memory cells each storing one-bit data. Each memory cell is located at a certain address designated by a row address and a column address.
Row decoders
36
a
-
36
d
designate row addresses of memory arrays
35
a
-
35
d,
respectively in response to row address signals X
0
-Xj supplied from address buffer
33
. Column decoders
37
a
-
37
d
designate column addresses of memory arrays
35
a
-
35
d,
respectively in response to column address signals Y
0
-Yj supplied from address buffer
33
.
Sense amplifiers+input/output control circuits
38
a
-
38
d
connect memory cells at addresses designated by row decoders
36
a
-
36
d
and column decoder
37
a
-
37
d,
respectively, to one ends of data input/output line pairs IOPs. Another ends of data input/output line pairs IOPs are connected to data input/output circuit
39
. Data input/output circuit
39
supplies data input from an external source to a selected memory cell via data input/output line pair IOP in a writing mode, and supplies as an output data read from a selected memory cell to an external device in a reading mode.
FIG. 5
is a partially omitted circuit block diagram showing a structure of memory array
35
a
and sense amplifier+input/output control circuit
38
a
of SDRAM
30
shown in FIG.
4
.
With reference to
FIG. 5
, memory array
35
a
includes a plurality of memory cells MCs arranged in a matrix, word lines WLs arranged for respective rows, and bit line pairs BLs, /BLs arranged for respective columns.
Each memory cell MC is of a well known type in the art and includes an access N channel MOS transistor and an information storing capacitor. Word line WL transmits an output of row decoder
36
a
and activates a memory cell MC in a selected row. Bit line pair BL, /BL serves for input/output of a data signal to/from a selected memory cell MC.
Sense amplifier+input/output control circuit
38
a
includes column select gates
41
s,
sense amplifiers
42
s
and equalizers
43
s
arranged corresponding to respective columns. Column select gate
41
includes a pair of N channel MOS transistors connected between bit line pair BL, /BL and data input/output line pair IO, /IO. A gate of each N channel MOS transistor is connected to column decoder
37
a
via a column select line CSL. When column select line CSL is activated by column decoder
37
a
to an “H” (logical high) level which is a select level, a pair of N channel MOS transistors is rendered conductive coupling bit line pair BL, /BL and data input/output line pair IO, /IO.
Sense amplifier
42
amplifies a minor potential difference between bit line BL and bit line /BL to the level of power supply voltage Vcc in response to activation of sense amplifier activation signals SE, /SE respectively to an “H” level and to an “L” (logical low) level. Equalizer
43
equalizes the potentials of bit line BL and bit line /BL to a bit line voltage VBL (=Vcc/2) in response to activation of a bit line equalization signal BLEQ to an “H” level. Memory arrays
35
b
-
35
d
and sense amplifiers+input/output control circuits
38
b
-
28
d
are of the same structure as memory array
35
a
and sense amplifier+input/output control circuit
38
a.
Here, signals SE, /SE, BLEQ are included in command signals CMD
0
-CMDi shown in FIG.
4
.
Next, an operation of SDRAM
30
shown in
FIGS. 4 and 5
will be briefly described. In the writing mode, one of column decoders
37
a
-
37
d
activates column select line CSL in a column corresponding to column address signals Y
0
-Yj to an activation level, that is an “H” level, rendering column select gate
41
conductive.
Data input/output circuit
39
supplies data to be written supplied from an external source to a bit line pair BL, /BL of a selected column via data input/output line pair IOP. Data to be written is given as a potential difference between bit line BL and bit line /BL. Then, one of row decoders
36
a
-
36
d
activates word line WL of a row corresponding to row address signals X
0
-Xj to an “H” level, that is the select level, rendering an N channel MOS transistor of a memory cell MC in the row conductive. Electric charges of an amount corresponding to the potential of bit line BL or /BL is stored in the capacitor of the selected memory cell MC.
In the reading mode, first, bit line equalization signal BLEQ is pulled down to an “L” level and the equalization of bit lines BL and /BL is stopped. One of row decoders
36
a
-
36
d
pulls up a word line WL of a row corresponding to row address signals X
0
-Xj to an “H” level that is the select level. The potentials of bit lines BL and /BL change by a minor amount according to the amount of electric charges in a capacitor of an activated memory cell MC.
Then, sense amplifier activation signals SE and /SE attain an “H” level and “L” level, respectively and sense amplifier
42
is activated. When the potential of bit line BL is higher than the potential of bit line /BL by a minor amount, the potential of hit line BL is pulled up to an “H” level and the potential of bit line /BL is pulled down to an “L” level. Conversely, when the potential of bit line /BL is higher than the potential of bit line BL by a minor amount, the potential of bit line /BL is pulled up to an “H” level and the potential of bit line BL is pulled down to an “L” level.
One of column decoders
37
a
-
37
d
then activates column select line CSL of a column corresponding to column address signals Y
0
-Yj to an “H” level, that is the select level, rendering column select gate
41
of the column conductive. Data of bit line pair BL, /BL of the selected column is supplied to data input/output circuit
39
via column select gate
41
and data input/output line pair IO, /IO. Data input/output circuit
39
supplies read data to an external device.
To guarantee the quality of an SDRAM such as SDRAM
30
, a variety of tests are performed before delivery. Tests include long period test

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