Semiconductor memory device providing redundancy

Details Semiconductor memory device providing redundancy Semiconductor memory device providing redundancy

2006-06-13

2006-06-13

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189050

Reexamination Certificate

active

07061815

ABSTRACT:
An improved semiconductor memory device providing row/column redundancy. The device includes a plurality of data latches arranged in a row-column matrix connected to a set of bitlines/global bitlines interfacing to read/write circuitry, at least two redundant row/column connected to a redundant bitline/global bitline, a first device for providing a first faulty row/column address in said matrix, a second device for generating other faulty row/column addresses by incrementing or decrementing predetermined numbers from the address provided by the first means, a comparison circuitry receiving as its inputs the accessed row/column address and the faulty row/column addresses, and a control block connected to the said comparison circuitry that receives a control signal such that it enables/disables the redundant and/or other memory cell row/column depending upon signals received from said comparison circuitry and control signal for normal operation of the memory device.

REFERENCES:
patent: 5659551 (1997-08-01), Huott et al.
patent: 5742556 (1998-04-01), Tavrow et al.
patent: 6314030 (2001-11-01), Keeth

Affiliated with

Also associated with

Rating

Semiconductor memory device providing redundancy does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device providing redundancy, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device providing redundancy will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3677847