Semiconductor memory device providing reduced test time

Details Semiconductor memory device providing reduced test time Semiconductor memory device providing reduced test time

1993-03-02

1994-11-22

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

365 51, 365 63, 365190, 365206, G11C 700, G11C 2900

Patent

active

053674928

ABSTRACT:
In a memory cell array having a plurality of memory cells connected to store physical information levels different in adjoining pairs of complementary data lines, those pairs of the memory cells, with which are connected the memory cells for storing the physical information levels in an identical pattern, are connected with a plurality of input/output lines by a column select circuit, so that the plurality of memory cells may be caused to perform the writing operations simultaneously in a test mode by feeding an identical write signal to the plurality of input/output lines. In the test mode, moreover, the input write data are processed so that the physical information levels of adjoining memory cells to be simultaneously written in the plurality of memory cells may be coincident.
Since the information levels of the adjoining bits can be made physically identical or different by combining the address selection and the write data, it is possible to shorten the testing time.

REFERENCES:
patent: 4958325 (1990-09-01), Nakagome
patent: 4992985 (1991-02-01), Miyazawa
patent: 5091887 (1992-02-01), Asakura
patent: 5111433 (1992-05-01), Miyamoto
patent: 5136543 (1992-08-01), Matsuda
Nikkei Micro Device; Mar. 1, 1988; pp. 67-81 "16Mbit Dram Specifications close to finalization for '90 sample delivery".

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