Semiconductor memory device provided with test memory cell unit

Details Semiconductor memory device provided with test memory cell unit Semiconductor memory device provided with test memory cell unit

2005-05-03

2005-05-03

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S145000, C365S200000, C365S051000

Reexamination Certificate

active

06888766

ABSTRACT:
A semiconductor memory device includes a memory cell block composed of a memory cell unit having memory cells each containing a ferroelectric capacitor, and a test memory cell unit having test memory cells. The layout pattern of the test memory cells is identical to the layout pattern of the memory cells. The test memory cell unit is arranged close to a memory cell of a plurality of memory cells which is at a position where the ferroelectric capacitor is susceptible to degradation. The memory cell unit and test memory cell unit are subjected to a first cycling test consisting of N1cycles. Then, the test memory cell unit is subjected to a second cycling test consisting of N2cycles. The sum (N1+N2) of the number of cycles in the first and second cycling tests equals an assurance number of cycles T, where N1<N2.

REFERENCES:
patent: 4855956 (1989-08-01), Urai
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patent: 6515923 (2003-02-01), Cleeves
patent: 2001-077320 (2001-03-01), None
“Low-power High-sped LSI Circuits & Technology”, Realize Ltd., pp. 231-250.
“All About Non-Erasable IC Memory-FRAM”, K.K. Kogyo Chosakai, pp. 29-37.

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