Semiconductor memory device provided with I/O clamp circuit

Details Semiconductor memory device provided with I/O clamp circuit Semiconductor memory device provided with I/O clamp circuit

1998-07-16

2001-09-04

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including signal clamping

C365S189060, C365S189110, C365S189011

Reexamination Certificate

active

06285602

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device provided with an I/O clamp circuit. More specifically, the present invention relates to a semiconductor memory device including an I/O clamp circuit for clamping a pulled up or pulled down node of an I/O line pair for applying an output signal of a sense amplifier included in a DRAM to a preamplifier.
2. Description of the Background Art
FIG. 8
is a schematic circuit diagram of an I/O line clamp circuit in a conventional DRAM. Referring to
FIG. 8
, a plurality of sense amplifiers
10
are connected through a plurality of transfer gates
20
to one end of an I/O line pair. Transfer gate
20
is turned on and off in response to a column selection line signal. The other end of I/O line pair
21
is connected to an input of a preamplifier
12
. Preamplifier
12
amplifies a signal connected to I/O line pair
21
, as I/O line pair
21
is relatively long and hence has a large capacitance and sense amplifier
10
has small drivability. Preamplifier
12
is an analog circuit and therefore it is necessary to appropriately set an input bias. Therefore, a pull up circuit
30
is connected between I/O line pair
21
. Pull up circuit
30
is generally formed by a series connection of two MOS transistors. When a read signal, a write signal or a standby signal at a logical high (“H”) level is input to NOR gate
31
, pull up circuit
30
is turned off by an output from NOR gate
31
.
Further, a clamp circuit
40
is connected to I/O line pair
21
so that charges are not left on I/O line pair
21
due to negative bump of a power supply voltage in the standby state. Clamp circuit
40
includes a clamp signal generating circuit including an n channel MOS transistor
41
having relatively long channel length L and very small supplying capability and p channel MOS transistors
42
and
43
having relatively large supplying capability connected in series between a power supply and a ground, and two n channel MOS transistors
44
and
45
connected in series between the pair of I/O lines
21
. In the clamp generating circuit, two n channel MOS transistors are connected in series. However, the number of stages may be changed in accordance with the clamp voltage.
FIGS. 9A
to
9
D are time charts related to the operation of the I/O clamp circuit shown in FIG.
8
. The operation of the I/O clamp circuit shown in
FIG. 8
will be described with reference to
FIGS. 9A
to
9
D.
Referring to
FIG. 9A
, while the standby signal is at the “H” level, that is, in the standby state, potential of I/O line pair
21
is kept at 2 Vthp as shown in
FIG. 9D
by the function of clamp circuit
40
, provided that power supply voltage changes from Vcc1 to Vcc2 at time T1 and it changes from Vcc2 to Vcc1 at time T2.
Assuming that standby signal is switched from “H” to “L” level at time T3 and is activated, n channel MOS transistors
44
and
45
are turned off, the output from NOR gate
31
attains to the “HI” level and pull up circuit
30
operates. Accordingly, the potential of I/O line pair
21
attains to Vcc1−Vth.
When read signal represented by
FIG. 9B
attains to “H” level at time T4, pull up circuit
30
is turned off, a column selection line is selected and data of the selected sense amplifier
10
appears on I/O line pair
21
through transfer gate
20
. Input bias of preamplifier
12
is at an appropriate value (Vcc1−Vth).
An operation when power supply voltage Vcc fluctuates in the active state will be described. Assuming that power supply voltage Vcc changes from Vcc1 to Vcc2 at time T5, the potential of I/O line pair
21
rises to Vcc2−Vth by the function of pull up circuit
30
. When power supply voltage Vcc returns from Vcc2 to Vcc1 at time T6, I/O line pair
21
is kept at the potential of Vcc2−Vth as shown in
FIG. 9D
, as the pull up circuit
30
has single directivity, that is, it operates only in the direction of increasing the potential of I/O line pair
21
and clamp circuit
40
is not in operation. When a reading operation is performed at time T7, I/O line pair
21
is opened, referring to the potential Vcc2−Vth. Here, optimal input bias for preamplifier
12
is Vcc1−Vth, and therefore operation margin of preamplifier
12
will not be ensured.
Therefore, though the conventional clamp circuit is effective against fluctuation of Vcc in the standby state, it is not effective against fluctuation of Vcc in the active state.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a semiconductor memory device including an I/O clamp circuit capable of clamping a potential of an I/O line pair even in the active state.
Briefly stated, the present invention provides a semiconductor device including an I/O clamp circuit connected to an I/O line pair for applying an output signal from a sense amplifier to a preamplifier, in which a current mirror circuit is provided for clamping the potential of the I/O line pair at a prescribed potential in the active state.
Therefore, according to the present invention, even in the active state, the potential of the I/O line pair can be clamped by the I/O clamp circuit.
More preferably, the I/O clamp circuit includes a first transistor of a first conductivity type having a first electrode and an input electrode connected to a first reference potential and a current mirror circuit including second and third transistors of a second conductivity type connected to the first reference potential through the first transistor, for generating a clamp potential signal, and a clamp circuit including fourth and fifth transistors of the second conductivity type connected in series between a pair of I/O lines for clamping the I/O line pair in response to the clamp potential signal applied from the current mirror circuit.
More preferably, in the current mirror circuit, the second transistor has a first electrode connected to a second electrode of the first transistor and an input electrode and a second electrode connected to an input electrode of the third transistor, the third transistor has a first electrode connected to a node between the fourth and fifth transistors and a second electrode connected to the reference potential, and further, a constant current source is connected between the second electrode of the second transistor and a second reference potential.
A resistance may be connected in place of the constant current source.
Further, a sixth transistor for pulling up is diode connected between the first electrode of the third transistor and the first reference potential. Further, a coupling capacitor is connected between the first reference potential and the input electrodes of the second and third transistors. The voltage fluctuation of the clamp circuit can be better followed as the coupling capacitor is provided.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5239508 (1993-08-01), Nomura et al.
patent: 5260904 (1993-11-01), Miyawaki et al.
patent: 5369613 (1994-11-01), Matsui
patent: 5508966 (1996-04-01), Nakase
patent: 5642314 (1997-06-01), Yamauchi
patent: 2-103797 (1990-04-01), None
patent: 3-154291 (1991-07-01), None
patent: 4-115622 (1992-04-01), None
patent: 4-349297 (1992-12-01), None
patent: 6-068680 (1994-03-01), None
patent: 9-171697 (1997-06-01), None

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