Semiconductor memory device preventing malfunction during...

Details Semiconductor memory device preventing malfunction during... Semiconductor memory device preventing malfunction during...

2000-04-25

2001-09-04

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

Reexamination Certificate

active

06285617

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and, more specifically to a semiconductor memory device performing a CBR (CAS before RAS) refresh operation.
2. Description of the Background Art
Stored information is retained in a DRAM (Dynamic Random Access Memory) by accumulating electric charges in a capacitor provided in a memory cell. Accordingly, a refresh operation must periodically be performed to prevent disruption of the stored information by a leakage current. In the refresh operation, word lines provided correspondingly to rows of the memory cells are sequentially selected, and accumulated electric charges are read for all memory cells on the selected word lines and rewritten after amplification. Thus, a voltage at a storage node in the memory cell is reset at an initial value even if it has been reduced by the leakage current. By continuing to sequentially select all of the word lines, the stored information in all memory cells are reproduced, so that the stored information for the entire chip can be retained.
Here, assume that a maximum value of a refresh interval assuring prevention of data disruption for every memory cell is trefmx and the number of word lines is N. Then, a relationship of tcrf≦trefmx/N must be held to enable a refresh operation with a given refresh cycle tcrf corresponding to an interval between word lines in order to prevent disruption of stored information by a leakage current. Accordingly, if the number of word lines increases due to an increase in a storage capacity of memories, the refresh cycle must correspondingly be reduced. Thus, in a DRAM with a large storage capacity, a refresh cycle is ensured by increasing the number of word lines simultaneously selected during a refresh operation as compared with that during a normal reading/writing operation in order to increase the number of rows subjected to a single refresh operation.
There are two types of refresh operations: a refresh operation performed during a random access operation such as a reading/writing operation; and a refresh operation performed only for retaining stored information in a chip as performed during a battery backup period. Especially in the former refresh operation, a CBR (CAS before RAS) refresh has been widely used in terms of saving the number of terminals. In the CBR refresh, the start of the refresh operation is instructed by reversing the order of activating a row address strobe signal /RAS and a column address strobe signal /CAS, which are inherently control signals, with respect to the order during a normal reading/writing operation without providing a control signal dedicated to the refresh operation.
FIG. 14
is a schematic diagram showing a memory array
500
of a DRAM structured to select a greater number of word lines during the refresh operation than during a normal operation.
While not shown in the drawing, memory array
500
has a plurality of memory cells arranged in a matrix. Here, memory array
500
is of a 64-Mbit size addressed by address bits A
0
to A
12
of an address signal of 13 bits. Memory array
500
is divided into two regions
500
a
and
500
b
of the same size in a row direction. In each of regions
500
a
and
500
b
, word lines are provided correspondingly to rows of the memory cells.
For row selection, the last bit A
12
of the address signal is used for selecting one of regions
500
a
and
500
b
of the memory array. In each of regions
500
a
and
500
b
, one memory cell row is selected and a corresponding word line is activated in accordance with a combination of the remaining address bits A
0
to A
11
of 12 bits. Thus, the word lines corresponding to the same combination of signal levels of address bits A
0
to A
11
are provided in both of regions
500
a
and
500
b.
FIG. 14
representatively shows word lines WLa and WLb correspondingly designated by address bits A
0
to A
11
in regions
500
a
and
500
b
. Word drivers WDa and WDb are respectively provided for word lines WLa and WLb.
Word driver WDa receives a block selection signal RAD
12
set correspondingly to address bit A
12
, a word line activation signal RXT, and an address decode signal ADC activated in accordance with a combination of address bits A
0
to A
11
for driving word line WLa into a selection state when all of these signals are activated. For each of the other word lines provided in region
500
a
, a word driver is arranged which activates the corresponding word line in accordance with signals as in the case of word driver WDa.
On the other hand, word line driver WDb receives a block selection signal ZRAD
12
which is complementary to block selection signal RAD
12
in accordance with address bit A
12
as well as word line activation signal RXT and address decode signal ADC also applied to word driver WDa for operation.
During normal reading and writing operations, one of block selection signals RAD
12
and ZRAD
12
is activated (H level) in response to a signal level of address bit A
12
, and a word line corresponding to address bits A
0
to A
11
is activated in one of regions
500
a
and
500
b
. On the other hand, during a refresh operation, both of block selection signals ZRAD
12
and RAD
12
are activated (H level) regardless of the signal level of address bit A
12
. Thus, in this case, corresponding word lines are activated in regions
500
a
and
500
b
in accordance with a combination of address bits A
0
to A
11
. Accordingly, in memory array
500
, twice as many word lines are simultaneously activated during the refresh operation as compared with the case of the normal operation. Such a structure ensures a refresh cycle for the memory cell array with a large storage capacity.
FIG. 15
is a timing chart shown in conjunction with a row related operation during a normal operation of memory array
500
.
Referring to
FIG. 15
, /RAS is a row address strobe signal designating activation of a row related operation. /CAS is a column address strobe signal designating activation of a column related operation. A
12
represents a signal level of address bit A
12
, and control signals RASF and CAS are respectively inverted signals of row address strobe signal /RAS and column address strobe signal /CAS, obtained as outputs from a control signal.
A signal ZRASE is an inverted signal of control signal RASF, and a control signal RADE is a row address decode enable signal activated when a prescribed period of time is elapsed after activation of row address strobe signal /RAS in response to the start of the row related operation.
One of block selection signals ZRAD
12
and RAD
12
is activated in accordance with the signal level of address bit A
12
during the normal operation. Control signals RXT and S
0
N are respectively a word line activation signal and a sense amplifier activation signal. Activation timings for signals RXT and S
0
N are controlled such that the word line and the sense amplifier are suitably timed to be activated in response to the start of the row related operation.
A refresh control signal ZCBR is inactivated (H level) during the normal operation and activated (L level) for designating a refresh operation for CBR refresh. Thus, when refresh control signal ZCBR is activated, both of block selection signals ZRAD
12
and RAD
12
are activated (H level). When refresh control signal ZCBR is inactivated (H level), one of block selection signals ZRAD
12
and RAD
12
is activated (H level) in accordance with the signal level of address bit A
12
.
Thus, when row address strobe signal /RAS is activated and the row related operation starts at a time t
0
, responsively, control signals RASF and ZRASE are sequentially activated (level) and row address decode enable signal RADE, word line activation signal RXT and sense amplifier activation signal S
0
N are activated. Block selection signal ZRAD
12
corresponding to the signal level (L level) of address A
12
is activated (H level) in response to activation of row address decode enable signal RADE, and RAD
12
is maintained in an

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