Semiconductor memory device performing multi-bit Serial operatio

Details Semiconductor memory device performing multi-bit Serial operatio Semiconductor memory device performing multi-bit Serial operatio

1987-09-03

1989-05-30

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Signals

365194, G11C 700

Patent

active

048357430

ABSTRACT:
In a semiconductor memory device capable of nibble mode operation, the time period required from the time when CAS signal falls to the time when a data output buffer activating signal rises is made different at the time of a normal mode and at the time of a nibble mode, so that the time period required for reading out data in the nibble mode is reduced as compared with a conventional device.

REFERENCES:
patent: 4344156 (1982-08-01), Eator, Jr. et al.
patent: 4602353 (1986-07-01), Wawersig et al.
patent: 4675850 (1987-06-01), Kumanoya et al.
IEEE Journal of Solid State Circuits-vol. SC-18, No. 5; Oct. 1983.
INMOS Inc., "100 ns 64K Dynamic Ram Using Efficient Redundancy Techniques", as presented at ISSCC, Feb. 18, 1981.

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