Semiconductor memory device performing multi-bit Serial operatio

Static information storage and retrieval – Read/write circuit – Signals

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

365194, G11C 700

Patent

active

048357430

ABSTRACT:
In a semiconductor memory device capable of nibble mode operation, the time period required from the time when CAS signal falls to the time when a data output buffer activating signal rises is made different at the time of a normal mode and at the time of a nibble mode, so that the time period required for reading out data in the nibble mode is reduced as compared with a conventional device.

REFERENCES:
patent: 4344156 (1982-08-01), Eator, Jr. et al.
patent: 4602353 (1986-07-01), Wawersig et al.
patent: 4675850 (1987-06-01), Kumanoya et al.
IEEE Journal of Solid State Circuits-vol. SC-18, No. 5; Oct. 1983.
INMOS Inc., "100 ns 64K Dynamic Ram Using Efficient Redundancy Techniques", as presented at ISSCC, Feb. 18, 1981.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor memory device performing multi-bit Serial operatio does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device performing multi-bit Serial operatio, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device performing multi-bit Serial operatio will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2159005

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.