Semiconductor memory device of which prescribed state of operati

Details Semiconductor memory device of which prescribed state of operati Semiconductor memory device of which prescribed state of operati

1997-04-14

1998-03-10

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

365222, 36523006, G11C 2900

Patent

active

057269408

ABSTRACT:
In the semiconductor memory device in accordance with the present invention, when test mode is entered at WCbR+super V.sub.IH +address key timing, the test mode is terminated only at the WCbR+super V.sub.IH +address key timing. Therefore, when refresh is to be started in the test mode, erroneous entrance to another test mode can be prevented, ensuring highly reliable testing. Further, since it is not necessary to take into account the special condition to enter the refreshing operation in the test mode, formation of a test pattern is facilitated.

REFERENCES:
patent: 5467314 (1995-11-01), Miyazawa et al.
patent: 5596537 (1997-01-01), Sukegawa et al.
Ishihara et al., "Standard 4M Bit DRAM Having x1/x4 Structure Manufactured by Way of Trial, Mass Production Around 1989 Expected", Nikkei Electronics 1987. Apr, 6. (No. 418) pp. 149-163.

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