Semiconductor memory device, nonvolatile semiconductor...

Details Semiconductor memory device, nonvolatile semiconductor... Semiconductor memory device, nonvolatile semiconductor...

2000-07-18

2001-06-05

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S203000, C365S206000, C365S226000

Reexamination Certificate

active

06243313

ABSTRACT:

Semiconductor Memory Device, Nonvolatile Semiconductor Memory Device, and Their Data Reading Method
BACKGROUND OF THE INVENTION
The present invention relates to a technique which is especially effective when applied to a data reading system for a semiconductor memory device and, more particularly, to a technique which is effective when applied to a nonvolatile memory device (as will be simply referred to as the “flash memory”) capable of erasing the data stored in a plurality of nonvolatile memory cells, electrically simultaneously.
In a highly integrated semiconductor memory, such as a dynamic random access memory (DRAM), one of the techniques, which has been adapted to prevent power noise caused at the start of operation of a sense amplifier, is one in which a current source for the sense amplifier is constructed to include a pair of MOSFETs connected in parallel and having different channel lengths. At the time of drive of the sense amplifier, one (i.e., the MOSFET having a smaller channel length) of the paired MOSFETs is turned on at first, and the other MOSFET (i.e., the MOSFET having a larger channel length) is then turned on. This effectively reduces the power fluctuation caused at the start of operation of the sense amplifier and reduces the noise due to power fluctuation, thereby to reduce erroneous reading of the DRAM. One of the publications disclosing the aforementioned techniques is Japanese Patent Laid-Open No. 62-275385 (275385/1983).
In the DRAM, the open bit line system having a low noise resistance has been adopted at first, but this system has been replaced by the folded bit line system, which has an excellent noise resistance. When noise occurs in the memory array of the DRAM of this folded bit line system, in-phase noise is transmitted to a pair of bit lines connected with one CMOS latch type differential sense amplifier through a parasitic capacitance between the bit lines. The differential sense amplifier is insensitive to the in-phase noise component on the paired bit lines so that the potential change of the bit lines in response to the data stored in a selected memory cell is accurately detected by the differential amplifier even if the in-phase noise component is carried on the paired bit lines.
A bit line shield system is a known technique for preventing erroneous reading of data due to noise in the semiconductor memory of the open bit line system. In the bit line shield system, in order to prevent erroneous reading of data due to the transmission of noise through the parasitic capacitance between adjoining data lines, the data lines are selected alternately every other line at the data reading time, and the unselected data lines are fixed at a ground potential or a reference potential. As a result, the unselected data lines, set to the ground potential or the reference potential, function as shielded lines to prevent erroneous reading of data.
In recent years, meanwhile, the simultaneous erase type electrically erasable and programmable nonvolatile read only memory (also referred to as the “flash EEPROM” or the “flash memory”) is one of the nonvolatile memories which as been used as a memory medium for a portable personal computer, a portable telephone, a digital still camera or a flash memory card, and investigations and developments have been made for manufacturing a flash memory and for making a flash memory multivalue system.
In the flash memory, too, the open bit line system and the folded bit line system are employed. Examples of flash memories of the open bit system or the folded bit line system are disclosed in Japanese Patent Laid-Open Nos. 7-153286 (153286/1995), 7-57482 (57482/1995) corresponding to U.S. Pat. No. 5,446,690 and 9-35486 (35486/1997).
Meanwhile, a flash memory adopting the open bit line system and the bit line shielded system is disclosed in Japanese Patent Laid-Open No. 7-45087 (45087/1995) corresponding to U.S. Pat. No. 5,473,570.
SUMMARY OF THE INVENTION
We have investigated in detail the noise which occurs at the time of reading data in the simultaneous erase type nonvolatile memory device (flash memory) of the open bit line system and of the bit shielded reading system.
In a flash memory using, as memory cells, nonvolatile memory elements having control gates and floating gates, more specifically, the memory array, as shown in
FIG. 24
, includes: a plurality of memory cell columns MCC
1
to MCCn having a plurality of nonvolatile memory elements MC
1
, MC
2
, . . . , and MCn; a plurality of local drain lines LDL
1
to LDLn coupled to the drains of the memory cells of the memory cell columns MCC
1
to MCCn; a plurality of main data lines DL
1
to DLn provided correspondingly to the memory cell columns MC
1
to MCn; a plurality of local source lines LSL
1
to LSLn coupled to the drains of the memory cells of the memory cell columns MCC
1
to MCCn; a plurality of select MOSFETs Qs
1
for coupling the main data lines DL
1
to DLn and the local drain lines LDL
1
to LSLn respectively; and a plurality of select MOSFETs Qs
2
for coupling the local source lines LSL
1
to LSLn and a common source line CSL selectively. In the memory array thus constructed, we have conceived to make the common source line CSL of a metal layer so as to reduce the wiring resistance.
Since the common source line CSL intersects the data lines DL
1
to DLn in this case, it may be formed of a first metal layer made of an aluminum layer or the like, whereas the data lines DL
1
to DLn may be formed of a second metal layer. Since control signal lines SD
1
and SS
1
for feeding control signals for turning on/off the select MOSFETs Qs
1
and Qs
2
are arranged in the memory array, they are arrayed in a direction to intersect the data lines DL
1
to DLn at right angles so that the control signal lines SD
1
to SS
1
are formed of a third metal layer.
FIG. 25
is a conceptual diagram relating to the section of the device thus constructed. In
FIG. 25
, reference symbol M
1
designates the common source line CSL made of the first metal layer; symbol M
2
designates the data lines DL
1
to DL
3
made of the second metal layer; and symbol M
3
designates the control signal line SD
1
(SST) made of the third metal layer. These metal layers M
1
, M
2
and M
3
are insulated by insulating films. Here, these insulating films are omitted from
FIG. 25
so as to simplify the illustration. As a matter of fact, many other control signal lines are formed of the third metal layer over the memory mat including the memory cells, but are omitted to simplify the illustration.
We have found the following fact from the construction in which the common source line CSL of the first metal layer M
1
and the control signal line SD
1
(SST) of the third metal layer M
3
are arranged over and under the data lines DL
1
to DL
3
of the second metal layer M
2
. Even if the reading system (the bit line shield system) is adopted in which the data lines (DL
1
and DL
3
) are made to read data by selecting them while leaving the un-selected data lines (DL
2
, etc) at the ground potential or the like to function as the shielded lines, the change in the data line at the data “1” may be transmitted as noise to the data line of the data “0” through the parasitic capacitance C
1
and C
2
, or C
3
and C
4
between the selected data lines (DL
1
and DL
3
) and the first and third metal layers M
1
and M
3
, thereby to cause erroneous reading.
FIG. 26
shows the behavior in which noise is transmitted. Specifically, the noise to the data line DL
1
, from which the data “0” is to be read out, is transmitted by the potential change of the data line DL
3
to the data “1”. In
FIG. 26
, the waveform a shows the potential change of the data line DL
3
, from which the data “1” is to be read out, and the waveform b shows the potential change of the data line DL
1
, from which the data “0” is to be read out. In the waveform a, the first step a
1
is a change to the precharge level, and the second step a
2
is a change to a Vcc level, caused by the amplifying action of a sense amplifier SA being driven

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