Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-01-31
2006-01-31
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185050, C365S185230
Reexamination Certificate
active
06992930
ABSTRACT:
A method for driving a semiconductor memory device includes a memory array having a plurality of memory cells arranged in rows and columns. Each memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a source and a drain as diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges. The method includes the steps of: selecting a row line connected to the gate electrode of a memory cell to be selected; grounding a first column line connected to the source of the memory cell to be selected; and applying a first potential to a second column line and a second potential to a third column line at the same time.
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Hamaguchi Kohji
Iwata Hiroshi
Matsuoka Nobuaki
Morikawa Yoshinao
Nawaki Masaru
Dinh Son T.
Morison & Foerster LLP
Sharp Kabushiki Kaisha
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