Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-06-11
2003-11-25
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S195000, C365S233100, C365S230030
Reexamination Certificate
active
06654303
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, such as a DRAM or PSRAM (pseudo static RAM), which has a refresh control function, a method for controlling such a semiconductor memory device and an electronic information apparatus including the same semiconductor memory device.
2. Description of the Related Art
Conventionally, a DRAM/PSRAM requires a refresh operation for holding data therein. In the DRAM/PSRAM, a prescribed period of time is set so as to perform the refresh operation while inhibiting a CPU (central processing unit) from accessing the DRAM/PSRAM during the prescribed period of time.
However, for a system which is required to have fast processing ability, it is a great waste of time to set such a time period so as to inhibit the CPU from accessing memory, such as DRAM or PSRAM. In order to avoid such a great waste of time, for example, a “memory control device” disclosed in Japanese Laid-Open Patent Publication No. 7-161184 has been suggested. A control method used in this memory control device is described with reference to FIG.
6
.
FIG. 6
is a block diagram showing a primary structure of a conventional semiconductor memory device including a conventional memory control device as disclosed in Japanese Laid-Open Patent Publication No. 7-161184. In
FIG. 6
, a memory block is divided into a plurality of memory banks which are not accessed simultaneously. The conventional memory control device includes refresh timers each corresponding to a respective one of the plurality of memory banks. Each refresh timer measures a period of time elapsed since a corresponding memory bank was refreshed. The conventional memory control device also includes a timer comparison section for comparing respective values of the refresh timers so as to determine a memory bank, which has not been refreshed for the longest period of time, among all the memory banks.
When a read/write access operation is performed with respect to the memory bank due to an external control signal (not shown), a refresh operation is performed simultaneously with the read/write cycle on one of the memory banks other than the memory bank, which is targeted for the read/write access operation, corresponding to the refresh timer having a greatest value, i.e., the memory bank which has not been refreshed for the longest period of time among all the memory banks other than the target memory bank.
When only the same memory bank is continuously accessed so that the same memory bank cannot be refreshed during a period of time for data to be held by the same memory bank, the conventional memory control device outputs a timeout signal to the same memory bank so as to inhibit the same memory bank from being accessed and to refresh the same memory bank.
Therefore, a refresh operation can be concealed so as not to be apparent to any external device when continuous accesses are not performed with respect to the same memory bank.
However, since the DRAM/PSRAM are random access memories, only the same memory bank can be continuously accessed. As described above, in the structure of the conventional memory control device, when the same memory bank is continuously accessed, the conventional memory control device outputs a timeout signal so as to inhibit the same memory bank from being accessed, and therefore the refresh operation can be performed on the same memory bank. However, if the conventional memory control device frequently outputs the timeout signal (so as to perform the refresh operation), a period of time occurs for which the same memory bank is continuously inhibited from being accessed, and therefore there is no sense in employing the conventional control method as described above.
In order to reduce the frequency of outputting the timeout signal, a possibility that only the same memory bank is accessed must be decreased. One method applicable to this end is to subdivide the memory block so as to increase the division number of the memory block (i.e., the number of memory banks).
However, as described above, in the conventional control method used in conjunction with the “memory control device” disclosed in the Japanese Laid-Open Patent Publication No. 7-161184, the memory control device is required to include the refresh timers each corresponding to a respective one of the memory banks. Each refresh timer measures a critical amount of time for a memory cell to hold data. Although a size of each refresh timer is not considerably large, a size of a circuit, which includes a plurality of refresh timers according to the number of memory banks, becomes large. Further, since the timer comparison section is required to compare values of all the refresh timers, when the number of memory banks is increased, the timer comparison section becomes complex and large.
On the other hand, since the number of memory banks cannot be increased, a size of each memory bank is increased. That is, a region to be activated for each access is increased in the memory bank, thereby causing an increase in consumption current. Further, whenever a read/write access operation is performed with respect to the memory bank due to the external control signal, a refresh operation is performed on another memory bank. Accordingly, two memory banks are always activated simultaneously. Since these two memory banks are simultaneously activated, the refresh operation is concealed so as not to be apparent to any external device, i.e., the memory access and the refresh operation are simultaneously performed in parallel. However, when the memory bank is sequentially requested to be read/written every 100 nanoseconds, the refresh operation is also performed every 100 nanoseconds while it is enough to perform the refresh operation with a frequency between several microseconds and several tens of microseconds. As a result, consumption current is increased by the unnecessary refresh operations.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided a semiconductor memory device which includes: a memory block including a plurality of memory cells each including a transistor and a capacitor and storing information based on the presence of charges in the capacitor, the charges in the capacitor being held by a refresh operation, the memory block being divided into a plurality of memory banks such that the number of the memory banks is greater than a usually-prescribed number and the plurality of memory banks are not simultaneously accessed, the plurality of memory banks individually receiving access and refresh operations with respect to the memory cells; a time measurement section for measuring a critical amount of time for the memory cells to hold data; a plurality of memory circuits each storing refresh information which indicates that a corresponding memory bank is refreshed; a refresh address designation section for designating a refresh address in the corresponding memory bank; and a refresh control section for controlling the refresh operation with respect to each of the memory banks according to the designated refresh address and determining an unrefreshed memory bank based on the refresh information so as to perform the refresh operation with respect to the determined unrefreshed memory bank.
In one embodiment of this invention, the semiconductor memory device further includes a plurality of adjustment sections provided so as to respectively correspond to the memory banks and select any one of the refresh address and a normal access address based on a control signal from the refresh control section.
In one embodiment of this invention, the refresh control section controls an operation of the semiconductor memory device so as to inhibit access to a normal access address and prioritize the refresh operation with respect to the memory bank which is not refreshed within the critical amount of time for the memory cells to hold data.
In one embodiment of this invention, when normal access is performed with respect to the memory bank at a normal access ad
Miyamoto Yasuo
Takata Hidekazu
Auduong Gene N.
Ho Hoai
Sharp Kabushiki Kaisha
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