Semiconductor memory device internally generating internal...

Details Semiconductor memory device internally generating internal... Semiconductor memory device internally generating internal...

2003-05-28

2004-10-12

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S210130, C365S205000

Reexamination Certificate

active

06804153

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having data of a selected memory cell read internally using a sense amplifier. More specifically, the present invention relates to the configuration for optimizing an activation timing of the sense amplifier.
2. Description of the Background Art
There is known, as a semiconductor memory device, a static memory (SRAM: Static Random Access Memory) having internal circuitry operating statically. Since the internal circuitry of the SRAM operates statically, and a memory cell row and a memory cell column are selected substantially at the same time, the SRAM can ensure high speed access and is widely used for high speed processing.
FIG. 34
is a schematic diagram showing the configuration of a main part of a conventional SRAM. In
FIG. 34
, SRAM cells MC are arranged in rows and columns in a memory array. In
FIG. 34
, SRAM cells MC are arranged in (m+1) rows and (n+1) columns. Word lines WL
0
to WLm are arranged in correspondence to the respective rows of SRAM cells MC, and bit line pairs BL
0
, ZBL
0
to BLn, ZBLn are arranged in correspondence to the respective columns of SRAM cells MC.
Word line drivers WD
0
to WDm are arranged in correspondence to word lines WL
0
to WLm, respectively, and column select gates CSG
0
to CSGn are arranged in correspondence to bit line pairs BL
0
, ZBL
0
to BLn, ZBLn, respectively.
Word line drivers WD
0
to WDm, each of which is formed of an inverter, drive word lines WL
0
to WLm in accordance with word line select signals WX
0
to WXm generated on the basis of an X address signal, respectively. Accordingly, when selected, word line select signals WX
0
to WXn are at L level (logical low level) and a selected word line is driven to H level (logical high level).
Column select gates CSG
0
to CSGn are made conductive in accordance with column select signals Y
0
to Yn generated on the basis of a Y address signal, respectively, and couple corresponding bit line pairs BL
0
, ZBL
0
to BLn, ZBLn to an internal bus DB, respectively, when made conductive. Internal bus DB includes internal bus lines DBL and ZDBL transferring complementary data signals, respectively.
A sense amplifier SA that differentially amplifies signals on complementary data bus lines DBL and ZDBL of internal data bus DB, is provided to internal data bus DB. Sense amplifier SA differentially amplifies complementary data signals transferred from selected bit lines to internal data bus DB and generates internal read data DO in response to activation of a sense enable signal SE from a delay adjustment element DLE.
Delay adjustment element DLE, which is formed of, for example, cascaded delaying inverters, adjusts the delay time of a sense trigger signal SATR and generates sense enable signal SE. Sense trigger signal SATR applied to delay adjustment element DLE is generated on the basis of either a bit line precharge signal or a word line activation signal when data is read.
Sense amplifier SA is provided in correspondence to a predetermined number of bit line pairs. Specifically, this memory cell array is divided into a plurality of column blocks in accordance with the number of internal read data bits. Sense amplifiers SA are arranged in correspondence to the respective column blocks, and sense enable signal SE from delay adjustment element DLE is commonly applied to sense amplifiers SA which are arranged in correspondence to the respective column blocks. Now, the operation of the SRAM shown in
FIG. 34
in data read will be briefly described.
In accordance with an X address signal, one of word line select signals WX
0
to WXm is driven into a selected state. Word line WL designated by this X address signal is driven into a selected state by corresponding one of word line drivers WD
0
to WDm, and the stored data of SRAM cells MC connected to selected word line WL is read to corresponding bit line pairs BL
0
, ZBL
0
to BLn, ZBLn. SRAM cell MC has the configuration as will be described later, and stores complementary data at internal storage nodes, respectively. The potential of one bit line of each of bit line pairs BL
0
, ZBL
0
to BLn, ZBLn becomes lower than a precharge potential in accordance with L level data. Here, all of bit line pairs BL
0
, ZBL
0
to BLn, ZBLn are precharged to power supply voltage level in a standby state.
In SRAM, the X address signal and the Y address signal are applied in parallel. A column select operation is performed in parallel to a word line select operation. In accordance with the Y address signal, one of column select signals Y
0
to Yn is driven into a selected state, one of column select gates CSG
0
to CSGn corresponding to a selected column is made conductive responsively, and the bit line pair on the selected column are connected to data bus lines DBL and ZDBL of internal data bus DB, respectively.
When a certain time passes since selection of the word line, the potential difference between the selected bit lines is developed and the potential difference in internal data bus DB is developed accordingly and reaches a potential difference which can be sensed by sense amplifier SA. Delay adjustment element DLE adjusts the sense timing of sense amplifier SA. When the potential difference of internal data bus DB becomes sufficiently large, delay adjustment element DLE activates sense enable signal SE to start the sensing operation of sense amplifier SA. Sense amplifier SA differentially amplifies the complementary data signals on internal data bus DB and generates internal read data DO.
FIG. 35
shows an example of the configuration of sense amplifier SA shown in FIG.
34
. In
FIG. 35
, sense amplifier SA includes: cross-coupled P-channel MOS transistors (insulating gate field effect transistors) PQa and PQb; cross-coupled N-channel MOS transistors NQa and NQb; a P-channel MOS transistor PQc for coupling a sense node SNa to internal data bus line DBL in response to sense enable signal SE; a P-channel MOS transistor PQd for coupling a sense node SNb to an internal data bus line ZDBL in response to sense enable signal SE; and an N-channel MOS transistor NQc for coupling the sources of MOS transistors NQa and NQb to a ground node in accordance with sense enable signal SE.
P-channel MOS transistor PQa is connected between a power supply node and sense node SNa, and has a gate thereof connected to sense node SNb. P-channel MOS transistor PQb is connected between the power supply node and sense node SNb, and has a gate thereof connected to sense node SNb. N-channel MOS transistor NQa is connected between sense node SNa and MOS transistor NQc, and has a gate thereof connected to sense node SNb. N-channel MOS transistor NQb is connected between sense node SNb and MOS transistor NQc, and has a gate thereof connected to sense node SNa.
Internal data bus lines DBL and ZDBL are 1-bit data bus lines included in data bus DB shown in
FIG. 34
, and coupled to a selected bit line pair through the column select gate in data read, respectively.
Sense amplifier SA further includes a holding circuit HK for latching the signals at sense nodes SNa and SNb and generating internal read data DO. The operation of sense amplifier SA shown in
FIG. 35
will now be described with reference to a timing chart shown in FIG.
36
.
When data is read, bit lines BBL and ZBL are precharged to power supply voltage level by a bit line load circuit, not shown. In accordance with the X address signal, the potential of word line WL corresponding to an addressed row rises to H level, the data of memory cells MC connected to this selected word line is read to bit lines BL and ZBL. In SRAM cell MC, complementary data of H-level data and L-level data are stored in a pair of storage nodes, respectively. The bit line connected to the storage node storing the L-level data is discharged through the driver transistor of memory cell MC and the voltage level of the bit line is lowered.
In parallel to this word line

Affiliated with

Also associated with

Rating

Semiconductor memory device internally generating internal... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device internally generating internal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device internally generating internal... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3311379