Semiconductor memory device input circuit

Details Semiconductor memory device input circuit Semiconductor memory device input circuit

2002-03-27

2004-02-24

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S095000, C365S228000

Reexamination Certificate

active

06696862

ABSTRACT:

This application claims priority from Korean Patent Application No.
01-22982
, filed Apr. 27, 2001, herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device input circuit.
2. Description of the Related Art
The operation frequency of semiconductor memory devices is continuously improving with advances in the related technology. A setup/hold window during which data is input, consequently decreases. To address this issue, a method for tracking input data using a data strobe signal has been suggested for a double data rate (DDR) synchronous dynamic random access memory (SDRAM).
FIG. 1
is a circuit diagram of a semiconductor memory device input circuit
100
. Referring to
FIG. 1
, the input circuit
100
includes a plurality of input buffers
101
through
107
, a calibration circuit
109
, and a plurality of data registers
111
through
115
. One of the functions of the input circuit
100
is to store a plurality of input data D
0
through Di in the corresponding registers
111
through
115
, respectively, within a predetermined time.
The calibration circuit
109
is a signal transmission circuit for synchronizing different delay characteristics. The calibration circuit
109
generates a controlling clock signal for controlling the data strobe signal DQS responsive to a data strobe signal DQS. The calibration circuit
109
synchronizes the input data D
0
, D
1
through Di with different delay times according to an input path. The calibration circuit is explained in further detail in Korean Patent Application No.
10-2000-0035335
, incorporated herein by reference.
The input data D
0
, D
1
through Di, are transmitted to the corresponding registers with different delay times owing to the arrangement characteristics of circuits and elements. The controlling clock signal used in storing the input data in the corresponding registers is generated in the calibration circuit
109
responsive to the data strobe signal DQS. The controlling clock signal synchronizes with the input data such that the input data are stored in the corresponding registers within a predetermined time. Thus the plurality of input data D
0
through Di is stored in the corresponding registers
111
to
115
responsive to the signal output by the calibration circuit
109
.
The data strobe signal DQS is enabled responsive to an active write command (not shown). Thus, the signal DQS is not generated before a first write operation. And the controlling clock signal for storing the input data in the corresponding registers
111
through
115
within a predetermined time cannot be generated in the calibration circuit
109
using the data strobe signal DQS from the time the power is turned on to the first write operation.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the disadvantages associated with known semiconductor memory devices.
It is another object of the present invention to provide semiconductor memory device input circuit including a clock selection portion for preventing malfunction of the input circuit from the time when power is initially turned on to the time when a data strobe signal is enabled.
It is yet another object of the present invention to provide a method for selecting a clock signal implemented in the input circuit of a semiconductor memory device to prevent malfunction from the time when power is initially turned on to the time when a data strobe signal is enabled.
Accordingly, an input circuit for a semiconductor memory device is provided. The input circuit includes a plurality of input buffers adapted to buffer corresponding input data and a clock selection circuit adapted to generate a second clock signal by selecting between a first clock signal and a data strobe signal responsive to a selection signal, the selection signal being maintained at a first logic level for a predetermined time after power up. A calibration circuit is adapted to generate a register clock signal responsive to the second clock signal.
And a plurality of data registers is adapted to store buffered input data responsive to the register clock signal.
The clock selection circuit might output the first clock signal as a second clock signal when the selection signal is at a first logic level and the clock selection circuit might output the data strobe signal as the second clock signal when the selection signal is at a second logic level.
In one embodiment, the clock selection circuit includes a first PMOS transistor having a first end connected to a supply voltage and a gate adapted to receive the selection signal and a first buffer having a first input adapted to receive the data strobe signal, a second input adapted to receive a reference voltage, and a third input being connected to a second end of the first PMOS transistor. A first NMOS transistor has a first end connected to an output terminal of the first buffer, a second end connected to ground, and a gate adapted to receive the selection signal. A second buffer has a first input adapted to receive a first clock signal and a second input adapted to receive an inverted clock signal. An inverter has an input terminal connected to the output terminal of the first buffer. A first logic gate is adapted to logically manipulate the selection signal and an output signal of the second buffer. And a second logic gate is adapted to logically manipulate an output signal of the first logic gate and an output signal of the first inverter.
In one embodiment, the predetermined time is a time between power up and a mode register set signal being enabled.
In one embodiment, the predetermined time is a time between power up and the data strobe signal being enabled.
A method for selecting a clock signal in an input circuit for a semiconductor memory device is also provided. The method includes providing a first clock signal as a second clock signal responsive to a selection signal being in a first logic state, providing a data strobe signal as the second clock signal responsive to the selection signal being a second logic state, generating a register clock signal responsive to the second clock signal, and registering the input data responsive to the register clock.
The method might further include setting the selection signal to the second logic state a predetermined time after power up.
The method might further include setting the selection signal to the first logic state after enabling a mode set register signal and setting the selection signal to the second logic state after enabling the data strobe signal.


REFERENCES:
patent: 6061292 (2000-05-01), Su et al.
patent: 6069829 (2000-05-01), Komai et al.
patent: 2001/0055344 (2001-12-01), Lee et al.

Affiliated with

Also associated with

Rating

Semiconductor memory device input circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device input circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device input circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3346314