Semiconductor memory device incorporating redundancy memory cell

Details Semiconductor memory device incorporating redundancy memory cell Semiconductor memory device incorporating redundancy memory cell

1995-11-29

1996-10-29

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Bad bit

365203, 3652257, 36523003, 36523006, G11C 2900

Patent

active

055703186

ABSTRACT:
In a semiconductor memory device including a plurality of memory cell clocks each having a mormal memory cell array and first and second redundancy memory cell rows, one first redundancy row selecting circuit is provided for each of the memory cell blocks to access the first redundancy memory cell row upon receipt of a respective memory cell block selection signal, and one second redundancy row selecting circuit is provided for at least two of the memory cell blocks to access the second redundancy memory cell row upon receipt of a respective memory cell block selection signal.

REFERENCES:
patent: 5265055 (1993-11-01), Horiguchi et al.
patent: 5469388 (1995-11-01), Park
patent: 5485418 (1996-04-01), Hiraks et al.
patent: 5517450 (1996-05-01), Ohsawa

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