Semiconductor memory device incorporated with self-refresh circu

Details Semiconductor memory device incorporated with self-refresh circu Semiconductor memory device incorporated with self-refresh circu

1993-01-29

1994-03-15

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Data refresh

365236, G11C 700

Patent

active

052951103

ABSTRACT:
A DRAM incorporated with a self-refresh circuit is disclosed which includes at least one terminal (bonding pad) optionally supplied with a first or a second potential level, a row address buffer/decoder having an input node coupled to the terminal to receive the potential level thereof and energizing a first number of word lines when the input node is at the first potential level and a second number of word lines when the input node is at the second potential level, a gate circuit inserted between the terminal and the input node of the address buffer/decoder and activated in the self-refresh mode to hold the input node at the first potential irrespective of the potential level of the terminal, a refresh timer activated in the slef-refresh mode for generating a refresh request signal in a predetermined cycle, and a refresh controller responding to the refresh request and refreshing memory cells connected to the energized first number of word lines.

REFERENCES:
patent: 4716551 (1987-12-01), Inagaki
patent: 4989183 (1991-01-01), Kumanoya et al.
1990 IEEE International Solid-State Circuits Conference, pp. 230, 231 and 303, Konishi et al., "A 38 ns 4 Mb DRAM with a Battery Back-Up (BBU) Mode".

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