Semiconductor memory device including spare memory cell

Details Semiconductor memory device including spare memory cell Semiconductor memory device including spare memory cell

2000-11-29

2002-01-01

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S203000, C365S225700, C365S230060

Reexamination Certificate

active

06335886

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and more particularly to a semiconductor memory device including a spare memory cell for replacing a defective memory cell.
2. Description of the Background Art
In recent years, memory ICs such as dynamic random access memories (hereinafter, referred to as DRAMs) have come to have higher storage capacity of a memory device and higher integration of components. Therefore, it has become difficult to ensure a yield of at least a prescribed level by a method in which the entire memory IC is regarded as defective if only one of a plurality of memory cells is defective. Consequently, a method of repairing a memory IC having a defective memory cell by providing a redundancy circuit in the IC has been generally employed.
According to the method, a spare memory cell is previously formed in a memory IC and, if a defective memory cell is encountered, the defective memory cell is replaced by the spare memory cell to repair the memory IC having the defective memory cell. In this method, a defective memory cell is replaced by a spare memory cell in a memory IC which has completed its wafer process, and thus replacement is generally carried out by blowing a fuse. Although a fuse is blown by an electric fuse method of blowing a fuse using an overcurrent, a laser blow method of blowing a fuse using a laser beam, and the like, the laser blow method allowing a higher degree of freedom for designing is generally employed.
FIG. 9
is a circuit block diagram showing a configuration of a redundancy row decoder in a DRAM for which such a redundancy method is employed. In
FIG. 9
, the redundancy row decoder includes fuses
50
a
to
50
d
, N channel MOS transistors
51
a
to
51
d
,
52
,
53
, a P channel MOS transistor
54
, and a word driver
55
.
P channel MOS transistor
54
is connected between a line of a power supply potential VCC and a node N
50
, and has its gate receiving a precharge signal/PC. Signal/PC is in a logic low or L level active state in a standby mode, and in the L level active state for a prescribed time period before word line selection in an active mode. When signal/PC attains the L level active state, P channel MOS transistor
54
is rendered conductive and node N
50
is precharged to a logic high or H level.
Fuses
50
a
to
50
d
each have its one terminal connected to node N
50
. N channel MOS transistors
51
a
to
51
d
are connected between the other terminals of fuses
50
a
to
50
d
and a line of a ground potential GND, and have their gates receiving predecode signals X
0
to X
3
, respectively.
Here, the number of word lines is four for simplicity of the figure and description. Predecode signals X
0
to X
3
are previously allocated to the four word lines, respectively. Fuses
50
a
to
50
d
are also previously allocated to the four word lines, respectively. Each of fuses
50
a
to
50
d
is blown if a corresponding word line is defective and the word line is replaced by a spare word line SWL. Only one of fuses
50
a
to
50
d
can be blown.
When one signal (X
0
, for example) of signals X
0
to X
3
attains an H level active state, N channel MOS transistor
51
a
corresponding to signal X
0
is rendered conductive. If fuse
50
a
corresponding to signal X
0
has not been blown, node N
50
falls from an H level to an L level. Node N
50
remains to be at the H level if fuse
50
a
has been blown. A signal appearing on node N
50
serves as a hit signal &phgr;H. Hit signal &phgr;H is applied to the gate of N channel MOS transistor
53
through N channel MOS transistor
52
. The gate of N channel MOS transistor
52
receives power supply potential VCC. N channel MOS transistor
52
is provided to protect N channel MOS transistor
53
.
When hit signal &phgr;H is at an H level, N channel MOS transistor
53
is rendered conductive, and a word line selection signal &phgr;R is applied to a control node
55
a
of word driver
55
through N channel MOS transistor
53
. When hit signal &phgr;H is at an L level, N channel MOS transistor
53
is rendered non-conductive, and word line selection signal &phgr;R is not applied to word driver
55
. Word driver
55
raises spare word line SWL to an H level selected state in response to word line selection signal &phgr;R. On the other hand, when hit signal &phgr;H is at the H level, the four word lines are all fixed to an L level non-selected state. As a result, a word line corresponding to a row including a defective memory cell has been replaced by spare word line SWL.
Since the conventional redundancy row decoder has such a configuration as described above, leakage current is caused in a standby state from node N
50
, which is kept at the H level, through fuses
50
a
to
50
d
and N channel MOS transistors
51
a
to
51
d
to the ground potential GND line. Although the leakage current for one fuse is small, the overall leakage current is larger because the number of word lines, that is, the number of fuses has increased due to the recent higher storage capacity and higher integration in a memory IC. Since a lower operating current for a memory IC has been promoted on the other hand, the leakage current of a redundancy row decoder has come to have a level that cannot be ignored for the operating current.
SUMMARY OF THE INVENTION
Therefore, a major object of the present invention is to provide a semiconductor memory device having small leakage current.
According to one aspect of the present invention, a redundancy decoder includes: a precharge circuit activated before an address signal is applied, and charging its output node to a first potential; a fuse provided corresponding to each memory cell, having one terminal connected to the output node of the precharge circuit, and blown when a corresponding memory cell is defective; a plurality of transistors provided corresponding to each memory cell, connected in series between the other terminal of a corresponding fuse and a line of a second potential, and rendered conductive in response to the address signal allocated to the corresponding memory cell being applied; and a driver activating a spare memory cell when the output node of the precharge circuit has the first potential after the address signal is applied. Therefore, as compared with a conventional case where only one transistor is connected between the other terminal of the fuse and the line of the second potential, a resistance value between the other terminal of the fuse and the line of the second potential is larger during the precharge period and leakage current flowing through each fuse is smaller.
According to another aspect of the present invention, a redundancy decoder includes: a precharge circuit activated before an address signal is applied, and charging its output node to a first potential; a fuse provided corresponding to each memory cell, having one terminal connected to the output node of the precharge circuit, and blown when a corresponding memory cell is defective; a first transistor provided corresponding to each memory cell, having a first electrode connected to the other terminal of a corresponding fuse, and rendered conductive in response to the address signal allocated to a corresponding memory cell being applied; a second transistor connected between a second electrode of the first transistor and a line of a second potential, and rendered non-conductive while the precharge circuit is active; and a driver activating a spare memory cell when the output node of the precharge circuit has the first potential after the address signal is applied. As described above, while the precharge circuit is active, the second transistor is non-conductive and the second electrode of the first transistor is in a floating state. As compared with a conventional case where the second electrode of the first transistor is always connected to the line of the second potential, therefore, leakage current flowing through each fuse is smaller.
Preferably, the second transistor is provided commonly to the plurality of

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