Semiconductor memory device including Shadow RAM

Details Semiconductor memory device including Shadow RAM Semiconductor memory device including Shadow RAM

2002-09-03

2004-12-28

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S094000, C365S104000, C365S063000

Reexamination Certificate

active

06836428

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a Static Random Access Memory (SRAM), particularly to a Shadow RAM having a memory cell constituted by adding a ferroelectric capacitor to SRAM for reading and writing an SRAM cell at high speed when power is supplied and keeping nonvolatile storage in the ferroelectric capacitor when power is not supplied.
2. Description of the Prior Art
A conventional Static Random Access Memory (SRAM) includes a flip flop by two of inverters of CMOS as shown by, for example, a circuit diagram of FIG.
1
A. Further, drains of NMOS transistors Q
0
and Q
1
constituting the flip flop, are made to constitute storage nodes N
0
and N
1
. The two storage nodes N
0
and N
1
are connected to a negative bit line BLN and a positive bit line BLT via NMOS transistors Q
4
and Q
5
respectively functioning as transfer gates. Respective gates of the NMOS transistors Q
4
and Q
5
constituting the transfer gates, are connected to a common word line WL. The negative bit line BLN and the positive bit line BLT are paired and a sense amplifier, not illustrated, for comparing and amplifying voltages of the two bit lines, is connected therebetween.
Meanwhile, a Shadow RAM is constituted by adding ferroelectric capacitors to the storage nodes N
0
and N
1
of the above-described SRAM (hereinafter, simply referred to as SRAM).
FIG. 1B
is a circuit diagram of an example of a Shadow RAM described in Japanese Patent Laid-Open No. 2000-293989. Portions the same as those of SRAM shown in
FIG. 1A
are designated by the same notations and an explanation thereof will be omitted. According to the Shadow RAM, respective ends on one side of the ferroelectric capacitors F
0
and F
1
are connected to the two storage nodes N
0
and N
1
and both of ends on other side of the respective ferroelectric capacitors F
0
and F
1
are connected to a plate line PL. The plate line PL is connected to a plate line drive circuit outside of the drawing.
When power is supplied, the Shadow RAM is set to ½ of power source voltage Vcc, that is, Vcc/2 and reading and writing data executed in supplying power, are carried out similar to a conventional general SRAM. When power source is cut, there is carried out store operation of switching to shift data stored by the flip flop to polarizing directions of the ferroelectric capacitors F
0
and F
1
. In a store period of time, stored data is stored as directions of remanent polarization of the ferroelectric capacitors F
0
and F
1
by driving the plate line PL to Vcc/2 to Vcc, further to 0V while maintaining the word line W in an inactivated state. Further, when power source is started, there is carried out recall operation of switching to shift data held by the ferroelectric capacitors to the flip flop. In a recall period of time, data stored by the ferroelectric capacitors as remanent polarization is reproduced to the flip flop by starting the power source of the flip flow while maintaining the word line WL and the plate line P
1
in an inactivated state. In this way the Shadow RAM can function as a nonvolatile memory by which data stored by the flip flop is preserved even after having been subjected to cutting and restarting power source and in the meantime, reading and writing data can be carried out similar to the conventional SRAM.
In order to form such a Shadow RAM on a semiconductor substrate (silicon substrate), it is necessary to form the ferroelectric capacitor at a layer as upper as possible. Because in a ferroelectric capacitor, a ceramic thin layer is generally used as a dielectric insulating film between a lower electrode and an upper electrode and since the ferroelectric film is made of an oxide, when the ferroelectric film is exposed to a deoxidizing atmosphere, oxygen deficiency is brought about, resistance is reduced, leak current between electrodes is increased and a reduction in a ferroelectric polarizing amount, a reduction in a dielectric constant and a deterioration in other electric properties are brought about. Therefore, the ferroelectric capacitor is arranged at an uppermost layer of a multilayer wiring structure to be able to be formed after various metals of wiring layers have been formed such that the ferroelectric capacitor is not exposed to the deoxidizing atmosphere.
A sectional view of
FIG. 10
shows a section taken along a line AA′ of FIG.
11
A and respective views of
FIGS. 11A
,
11
B and
11
C and
FIGS. 12A and 12B
are views viewed along lines a through e of the sectional view. In
FIG. 10
, there is constructed a constitution in which a transistor level
300
formed with an MOS transistor is provided on a silicon substrate
1
and above the transistor level
300
, there are provided multilayers of wiring layers successively laminated and formed with a first interlayer insulating film
311
, a first wiring level
301
, a second interlayer insulating film
312
, a second wiring level
302
, a third interlayer insulating film
313
, a third wiring level
303
, a fourth interlayer insulating film
314
, a ferromagnetic capacitor level (a fourth wiring level)
304
, a fifth interlayer insulating film
315
, a fifth wiring level
305
, and a passivation film
316
.
FIG. 11A
shows the transistor layer
300
comprising an N-type diffusion layer
321
and a P-type diffusion layer
322
and polysilicon wirings of a gate electrode
323
and a word line (WL)
324
formed at the silicon substrate
1
.
FIG. 11B
shows the first wiring level
301
comprising a first relay wiring
326
connected to the respective diffusion layers
321
and
322
of the transistor layer
300
via a first plug
325
. Further, the plug connects the upper layer
326
and the lower layers
321
and
322
to each other by filling a conductive material to a contact formed at the interlayer insulating film.
FIG. 11C
shows the second wiring level
302
comprising a power source line (Vcc)
328
connected to the first wiring level
301
by a second plug
327
, a GND line
329
, a second word line (WL)
330
connected in parallel with the word line
324
of the transistor layer
300
to reduce resistance of a total of the word line, and a second relay wiring
331
connected to the first relay wiring
326
.
FIG. 12A
shows the third wiring level
303
comprising bit lines (BLN, BLT)
333
connected to the second wiring level
302
by a third plug
332
, a third relay wiring
334
connected to the second relay wiring
331
.
FIG. 12B
shows the fourth wiring level
304
comprising a ferroelectric capacitor
336
connected to the third relay wiring
334
by a fourth plug
335
, and the fifth wiring level
305
comprising a plate line (PL)
341
of an upper layer by a fifth plug
340
further thereabove. The ferroelectric capacitor
336
is constituted by a laminated layer structure of a lower electrode
337
, a ferroelectric insulating film
338
and an upper electrode
339
, the lower electrode
337
is connected to the third relay wiring
334
and the upper electrode
334
is connected to the plate line
341
.
In this way, according to the above-described Shadow RAM (hereinafter, referred to as conventional type Shadow RAM), in order that the ferroelectric capacitors
336
are connected to the respective storage nodes N
0
and N
1
of the NMOS transistors Q
0
and Q
1
constituting the inverters, there is formed a structure in which the transistor layer
300
is connected to the lower electrode
337
of the ferroelectric capacitor
336
via the first through the fourth interlayer insulating films
311
through
334
. That is, respectives of the first through the third wiring level
301
through
303
are formed with the first through the third relay wirings
326
,
331
and
334
and the first through the fourth interlayer insulating films
311
through
314
are formed with the plugs
325
,
327
,
332
and
335
.
In this way, according to the Shadow RAM, the first through third wiring levels
301
through
303
, there is needed a space for arranging the respective relay wirings
326
,
331

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