Semiconductor memory device including serial/parallel...

Details Semiconductor memory device including serial/parallel... Semiconductor memory device including serial/parallel...

2001-03-23

2001-12-04

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Sipo/piso

C365S220000, C365S221000

Reexamination Certificate

active

06327206

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory that inputs and outputs multiple bit data in a serial manner.
A semiconductor memory device has a serial interface to transfer memory data and address data in a serial manner between the semiconductor memory device and an external device. A semiconductor memory device that performs such serial transfer has a relatively small number of data input/output (I/O) terminals and is thus compact. However, it takes time for such semiconductor memory device to input and output data.
FIG. 1
is a schematic block diagram of a prior art semiconductor memory device
10
. A memory cell array
1
includes a plurality of memory cells, which are arranged in a matrix-like manner, and selection circuits, each of which is provided for each row and each column to selectively activate each memory cell. The address decoder
2
responds to parallel address data AD-P having a predetermined number of bits and selectively activates certain rows and columns in the memory cell array
1
. A sense amplifier
3
is connected to each row of the memory cell array
1
to generate parallel read data RD-P from the data stored in the activated memory cell. A write amplifier
4
is connected to each column of the memory cell array
1
to write data to the activated memory cell.
A command decoder
5
controls the memory cell array
1
in response to command data CC-P. For example, when the command data CC-P instructs data reading, the command decoder
5
operates the memory cell array
1
in a read mode and connects the activated memory cell to the sense amplifier
3
. Further, when the command data CC-P instructs data writing, the command decoder
5
operates the memory cell array
1
in a write mode and connects the activated memory cell to the write amplifier
4
. The command decoder
5
may also set the deletion unit of the memory cells and the switch the number of bits of the stored data.
A data converter
6
converts serial address data AD-S, which is provided from an input/output (I/O) circuit
7
, to the parallel address data AD-P and provides the parallel address data AD-P to the address decoder
2
. In the read mode, the data converter
6
converts the parallel read data RD-P, which is provided from the sense amplifier
3
, to serial read data RD-S and provides the read data RD-S to the I/O circuit
7
. In the write mode, the data converter
6
converts serial write data WD-S to parallel write data WD-P and provides the parallel write data WD-P to the write amplifier
4
. Further, the data converter
6
converts serial command data CC-S, which is provided from the I/O circuit
7
, to parallel command data CC-P and provides the parallel command data CC-P to the command decoder
5
. The I/O circuit
7
is connected to the data converter
6
and transfers the read data RD-S, the write data WD-S, the address data AD-S, and the command data CC-S between the data converter
6
and an external device (not shown).
The memory cell array
1
, the address decoder
2
, the sense amplifier
3
, the write amplifier
4
, the command decoder
5
, the data converter
6
, and the I/O circuit
7
are fabricated on a semiconductor substrate. Further, the I/O circuit
7
has I/O terminals connecting the semiconductor memory device
10
to an external device. The input terminals receive each piece of data one bit at a time in a serial manner. Accordingly, the number of terminals need not be increased even if the number of bits in each piece of address data or stored data increases.
The data converter
6
is connected to the I/O circuit
7
by wires, the number of which is required to transfer one bit of data. The data converter
6
is further connected to the address decoder
2
, the sense amplifier
3
, the write amplifier
4
, and the command decoder
5
by wires, the number of which corresponds to the number of bits in each piece of data. An increase in the capacity of the memory cell array
1
increases the distance from the data converter
6
to the address decoder
2
, the sense amplifier
3
, the write amplifier
4
, or the command decoder
5
. This lengthens the wires connecting the data converter
6
to the address decoder
2
, the sense amplifier
3
, the write amplifier
4
, and the command decoder
5
. Further, these wires, the number of which corresponds to the number of bits in each piece of data, are arranged in parallel. This increases the area occupied by the wires. An increase in the wiring area enlarges the integrated circuit chip and restricts the layout of circuits on the chip.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device having reduced wiring area.
To achieve the above object, the present invention provides a semiconductor memory device including a memory cell array having a plurality of memory cells arranged in a matrix-like manner. An address decoder is connected to the memory cell array to selectively activate a certain memory cell in the memory cell array based on parallel address data. A sense amplifier generates parallel read data from data stored in the activated memory cell. An input/output circuit receives serial address data and outputs serial read data. A first serial/parallel converter is connected between the address decoder and the input/output circuit to convert the serial address data, which is received from the input/output circuit, to parallel address data and provide the parallel address data to the address decoder. The first serial/parallel converter is adjacent to the address decoder. A parallel/serial converter is connected between the sense amplifier and the input/output circuit to convert the parallel read data, which is received from the sense amplifier, to the serial read data and provide the serial read data to the input/output circuit. The parallel/serial converter is adjacent to the sense amplifier.
The present invention further provides a semiconductor memory device including a memory cell array having a plurality of memory cells arranged in a matrix-like manner. An input/output circuit receives serial address data, serial command data, and serial write data and outputs serial read data. An address decoder is connected to the memory cell array for selectively activating a memory cell in the memory cell array based on parallel address data. A first serial/parallel converter is connected between the input/output circuit and the address decoder to convert the serial address data, which is received from the input/output circuit, to the parallel address data and provide the parallel address data to the address decoder. The first serial/parallel converter is adjacent to the address decoder. A sense amplifier generates parallel read data from data stored in the activated memory cell. A parallel/serial converter is connected between the input/output circuit and the sense amplifier to convert the parallel read data, which is received from the sense amplifier, to the serial read data and provide the serial read data to the input/output circuit. The parallel/serial converter is adjacent to the sense amplifier. A command decoder is connected to the memory cell array to control the memory cell array based on parallel command data. A second serial/parallel converter is connected between the input/output circuit and the command decoder to convert the serial command data, which is received from the input/output circuit, to the parallel command data and provide the parallel command data to the command decoder. The second serial/parallel converter is adjacent to the command decoder. A write amplifier receives parallel write data and writes data to the memory cell activated by the address decoder. A third serial/parallel converter is connected between the write amplifier and the input/output circuit to convert the serial write data, which is received from the input/output circuit, to the parallel write data and provide the parallel write data to the write amplifier. The third serial/parallel conv

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