Semiconductor memory device including reference memory cell...

Static information storage and retrieval – Systems using particular element – Magnetoresistive

Reexamination Certificate

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C365S209000, C365S171000

Reexamination Certificate

active

06999340

ABSTRACT:
A semiconductor memory device includes word lines, bit lines, first memory cells, second memory cells, a memory cell array, a row decoder, a row driver, a column decoder, a column driver, and a sense amplifier. The first memory cell includes a magneto-resistive element which has either a first resistance or a second resistance smaller than the first resistance. The second memory cell includes a magneto-resistive element which has a resistance between the first and second resistances. The memory cell array includes the first and second memory cells disposed in intersections of the word line and bit line. The row driver supplies a first write current to the word line. The column driver supplies a second write current to the bit line. The sense amplifier amplifies data read from the first memory cell.

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patent: 6081445 (2000-06-01), Shi et al.
patent: 6317376 (2001-11-01), Tran et al.
patent: 6680863 (2004-01-01), Shi et al.
patent: 2003/0031046 (2003-02-01), Hidaka
patent: 2003242771 (2003-08-01), None
R. Scheuerlein, et al., IEEE International Solid-State Circuits Conference, Digest paper, pp. 128-129, “TA 7.2 A 10NS Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cell”, 2000.
M. Durlam, et al., IEEE International Solid-State Circuits Conference, Digest Paper, pp. 130-131, “TA 7.3 Nonvolatile RAM Based on Magnetic Tunnel Junction Elements”, 2000.

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