Semiconductor memory device including redundant memory cell arra

Details Semiconductor memory device including redundant memory cell arra Semiconductor memory device including redundant memory cell arra

1992-12-09

1995-05-16

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 36523003, 371 102, G11C 700

Patent

active

054167400

ABSTRACT:
An SRAM disclosed herein includes 64 memory cell array blocks and a redundant memory cell array block. The redundant memory cell array includes a total of 16 redundant memory cell columns. A defect address indicating a location of a defective memory column is programmed in an address programming circuit, and the specific defecting column in the defect address is programmed in an I/O programming circuit. Although each memory cell does not include a spare memory cell column or row for redundancy, the defect can be repaired by using a redundant memory cell array, so that the high integration of the SRAM can be accomplished.

REFERENCES:
patent: 4744060 (1988-05-01), Okajima
patent: 4817056 (1989-03-01), Furutani et al.
patent: 4935899 (1990-06-01), Morigami
patent: 5091884 (1992-02-01), Kagami
patent: 5132937 (1992-07-01), Tuda et al.
patent: 5157628 (1992-10-01), Tani

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