Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2003-06-06
2004-10-12
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S230030
Reexamination Certificate
active
06804154
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device including a power generation circuit for supplying an array power supply voltage and a peripheral power supply voltage respectively to a memory array and a peripheral circuit.
2. Description of the Background Art
To implement a stable and high-speed operation in a semiconductor memory device, a memory array is divided into a plurality of memory blocks which are arranged with sense amplifier circuits on both sides thereof, whereby each bit line pair is shortened to decrease the load thereof to transmit memory cell data having a sufficient voltage level to the sense amplifier circuit at high speed in order to accelerate a sense operation.
In such a structure, a power supply voltage and a ground voltage are supplied to the sense amplifier circuit to sense and amplify memory cell data of a corresponding column. When the power supply voltage and the ground voltage are transmitted for a long distance, levels of the power supply voltage and the ground voltage vary due to a wire resistance of a power supply line supplying the power supply voltage, which makes it impossible to perform an accurate sense operation. In addition, the power supply voltage cannot be supplied to the sense amplifier circuit at high speed due to the wire resistance. When a voltage level of an array power supply voltage decreases, a voltage level transmitted to a power supply node of the sense amplifier decreases and an operation speed of the sense amplifier decreases, which also causes degradation in sensitivity. If a sense margin decreases due to the degraded sensitivity, an accurate sense operation of the memory cell data may be inhibited.
To prevent such a decrease in sense margin and stably supply the sense power supply voltage and the ground voltage to the sense amplifier circuit, a mesh power supply arrangement is used in which power supply lines and ground lines are arranged in a mesh structure over a memory array.
In the mesh power supply arrangement, however, a power supply circuit is provided on one side of the memory block, and a distance from the power supply circuit to each memory cell in the memory block differs. Therefore, there is a difference in values of equivalent resistances of power supply lines, and thus the amounts of power supply voltage drops differ. For a memory cell located at the most distant point from the power supply circuit, for example, the wire resistance of the power supply line becomes the largest, and thus a desired power supply voltage cannot be supplied. Therefore, a margin to an array operation becomes smaller due to the voltage drop caused by the wire resistance of the power supply line, and thus the stable operation cannot be ensured.
One of the solutions for such a problem is to increase a wire width of the power supply line to decrease the resistance. By increasing the wire width, however, a dimension of the circuit undesirably increases, or a degree of freedom for a layout is limited.
Thus, recently, a semiconductor memory device as described in Japanese Patent Laying-Open No. 2001-256781, for example, has been suggested which includes a structure such that, a power supply driver is arranged near a sense power supply line of each of a plurality of sense amplifier bands, and a current is supplied from a power supply node to the sense power supply line of the corresponding sense amplifier band during an operation of the corresponding sense amplifier band. With this, a current can be supplied to the sense power supply line at high speed, and a decrease in a sense power supply voltage can be suppressed.
A semiconductor memory device as described in Japanese Patent Laying-Open No. 11-203862, for example, has also been suggested which includes a structure such that, a rectangular semiconductor substrate region is divided into subregions having a plurality of rows and a plurality of columns, and a control circuit is arranged in a central region, while a memory array block is arranged in a remaining region surrounding the central region. In such an arrangement structure, a peripheral power supply circuit is arranged in the central region, which allows to supply a power supply voltage to each memory array block with a minimum interconnection length, and to suppress an effect of voltage drop due to a wire resistance of a power supply line. In addition, a sense amplifier power supply circuit is arranged extending in a relatively large region around the memory array block region on either side of the semiconductor substrate region in one direction. The sense amplifier power supply circuit includes a decoupling capacity having a large capacity value to compensate for a large current consumption which flows during a sense amplifier operation and to suppress a significant sense amplifier power supply voltage. Therefore, by arranging the sense amplifier power supply circuit in a peripheral region having a larger area, a decoupling capacity requiring the larger area can be formed with a sufficient margin, and the sense amplifier power supply voltage can stably be generated.
The former of the semiconductor memory devices, however, cannot suppress an increase in a circuit dimension involved in the power supply driver arrangement, because the power supply driver must be arranged corresponding to each of the plurality of sense amplifier bands to stably supply the sense power supply voltage.
In the latter of the semiconductor memory devices, as a region having the same size as the divided memory block arrangement is kept as a control circuit formation region, and as the sense amplifier power supply circuit occupying a large area is further arranged in the peripheral region, the area of the circuit undesirably increases while the stable and high-speed operation is implemented.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device implementing a stable and high-speed array operation by suppressing a decrease in a power supply voltage without involving a increase in a circuit dimension.
A semiconductor memory device according to the present invention includes a memory array including a plurality of memory blocks each having a plurality of memory cells arranged in columns and rows, and the plurality of memory blocks are arranged aligned in a row direction and a column direction. The semiconductor memory device includes an array power generation circuit provided corresponding to each memory block for generating an array power supply voltage transmitted to the plurality of memory cells based on a first reference voltage, an array power supply line for supplying the array power supply voltage to the memory block, a peripheral power generation circuit provided corresponding to each memory block for generating a power supply voltage based on a second reference voltage at a same potential as the first reference voltage for a peripheral circuit included in each of the corresponding memory block and performing an operation for a memory cell selection, a peripheral power supply line for supplying the power supply voltage for the peripheral circuit to the peripheral circuit, and a connection transistor for electrically coupling the array power supply line to the peripheral power supply line.
As described above, in the semiconductor memory device according to the present invention, when the array power supply voltage has the same reference voltage as the peripheral power supply voltage, the array power supply line and the peripheral power supply line transmitting respective power supply voltages are electrically coupled using the connection transistor, whereby a voltage drop of the array power supply voltage due to the wire resistance can be mitigated and a stable array operation can easily be implemented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present inventi
Hamamoto Takeshi
Kitagawa Makoto
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