Semiconductor memory device including MOS transistor having...

Details Semiconductor memory device including MOS transistor having... Semiconductor memory device including MOS transistor having...

2005-09-06

2005-09-06

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S230060, C365S185330

Reexamination Certificate

active

06940762

ABSTRACT:
A semiconductor memory device includes a column decoder and a first row decoder. The column decoder or first row decoder includes a level shift circuit having a second to fifth transistor and a first switch element. The second and third MOS transistors have source connected electrically to a power supply potential. The fourth MOS transistor has a gate receiving an input signal, drain connected to a drain of the second MOS transistor and to the gate of the third MOS transistor, and the source connected to the ground potential. The fifth MOS transistor has a gate receiving the inverted input signal, drain connected to a drain of the third MOS transistor, to the gate of the second MOS transistor and to a bit line or word line. The first switch element controls the supply of the power supply potential to the second and third MOS transistors.

REFERENCES:
patent: 6222774 (2001-04-01), Tanzawa et al.
patent: 6384808 (2002-05-01), Azami
patent: 6510089 (2003-01-01), Taura et al.
Toru Tanzawa, et al., “Circuit Technologies for a Single-1.8V Flash Memory”, Symposium on VLSI Circuits Digest of Technical Papers, Jun. 1997, pp. 63-64.
Non-volatile Semiconductor Workshop 4.1, 1997, Wei-Hua Liu et al., “A2-Transistor Source-select (2TS) Flash EEPROM for 1.8V-Only Applications”.

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