Semiconductor memory device including memory cell transistors fo

Details Semiconductor memory device including memory cell transistors fo Semiconductor memory device including memory cell transistors fo

1995-07-12

2000-01-25

Monin, Jr., Donald L.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257304, 257350, H01L 27108

Patent

active

060181729

ABSTRACT:
A semiconductor memory device includes an SOI substrate, a plurality of word lines, a plurality of bit line pairs, a plurality of memory cells and a plurality of body fixing lines. The plurality of word lines are disposed in the row direction on the SOI substrate. The plurality of bit line pairs are disposed in the column direction on the SOI substrate. The plurality of memory cells are located on the SOI substrate and each are disposed correspondingly to one of crossings between the plurality of word lines and the plurality of bit line pairs. Each of the plurality of memory cells includes a capacitor and a transistor. The transistor is connected between the capacitor and one bit line in the corresponding bit line pair. The transistor is turned on in response to the potential of the corresponding word line. The plurality of body fixing lines are disposed on the SOI substrate. The plurality of body fixing lines are supplied with a predetermined potential. The transistors in the plurality of memory cells have source regions, drain regions and body regions located between the source and drain regions. The body regions of the transistors in the plurality of memory cells are connected to the plurality of body fixing lines.

REFERENCES:
patent: 3851317 (1974-11-01), Kenyon
patent: 4946799 (1990-08-01), Blake et al.
patent: 4965213 (1990-10-01), Blake
patent: 5079605 (1992-01-01), Blake
patent: 5125007 (1992-06-01), Yamaguchi et al.
patent: 5196910 (1993-03-01), Moriuchi et al.
patent: 5243209 (1993-09-01), Ishii
patent: 5245205 (1993-09-01), Higasitani et al.
patent: 5250831 (1993-10-01), Ishii
patent: 5274598 (1993-12-01), Fujii et al.
patent: 5332923 (1994-07-01), Takeuchi
patent: 5406102 (1995-04-01), Oashi
patent: 5442212 (1995-08-01), Eimori
patent: 5500815 (1996-03-01), Takase et al.
patent: 5528062 (1996-06-01), Hsieh et al.
patent: 5535153 (1996-07-01), Saeki
patent: 5555519 (1996-09-01), Takashima et al.
patent: 5592009 (1997-01-01), Hidaka
patent: 5604707 (1997-02-01), Kuge et al.
patent: 5635744 (1997-06-01), Hidaka et al.
Cavaliere et al., Reduction of Capacitive Coupling Between Adjacent Dielectrically Supported Conductors, IBM Technical Disclosure Bulletin vol. 21, No. 12, p. 4827, May 1979.

Affiliated with

Also associated with

Rating

Semiconductor memory device including memory cell transistors fo does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device including memory cell transistors fo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device including memory cell transistors fo will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2317607