Semiconductor memory device including ferroelectric memory...

Details Semiconductor memory device including ferroelectric memory... Semiconductor memory device including ferroelectric memory...

2003-03-28

2004-11-09

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S182000, C257S202000

Reexamination Certificate

active

06816399

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-097887, filed Mar. 29, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a ferroelectric memory using a ferroelectric capacitor.
2. Description of the Related Art
Semiconductor memories are now being used everywhere such as for the main storages of large-sized computers, personal computers, household electrical appliances, portable telephones, etc. Semiconductor memories on the market include volatile DRAMs (Dynamic RAMs) and SRAMs (Static RAMs), and nonvolatile MROMs (Mask ROMs), Flash EEPROMs and ferroelectric memories, etc.
Ferroelectric memories utilize a hysteresis characteristic that is one of the characteristics of a ferroelectric, i.e., utilizes the difference between the two residual polarization amounts of each ferroelectric capacitor, thereby storing binary data in a nonvolatile state. In general, each of the memory cells that provide a conventional ferroelectric memory is formed by connecting a capacitor (ferroelectric capacitor) to a transistor in series, as in a DRAM.
However, unlike DRAMs, it is necessary in ferroelectric memories to drive a plate line in order to read a signal charge to a bit line, since data is stored using a residual polarization amount difference. To this end, ferroelectric memories require a plate line driving circuit for driving a plate line. Further, since conventional ferroelectric memories have the same structure as DRAMs, plate line driving circuits are provided for respective plate lines. Accordingly, the plate line driving circuits occupy a large part of a memory circuit forming area.
On the other hand, a cell array method for use in ferroelectric memories has been proposed which can reduce the area required for the plate line driving circuits (D. Takashima et al., “High-density chain Ferroelectric random memory (CFeRAM)” in proc. VLSI Symp. June 1997, pp 83-84). In this case, the source and drain of a cell transistor (T) are connected to the opposite ends of a ferroelectric capacitor (C), thereby forming a unit cell (memory cell) MC. A plurality of such unit cells are connected in series, thereby forming a memory cell block. The thus-constructed ferroelectric memory will hereinafter be referred to as a “series connected TC unit type ferroelectric memory”.
In the series connected TC unit type ferroelectric memory, eight unit cells, for example, can commonly use one plate line driving circuit. Therefore, the memory cell array formed of a plurality of memory cell blocks can be highly integrated.
FIG. 1A
is a circuit diagram illustrating a memory cell array employed in the series connected TC unit type ferroelectric memory.
FIG. 1B
is a plan view illustrating the layout of the memory cell array.
Each unit cell MC is formed of the cell transistor T and ferroelectric capacitor C connected in parallel. In the case of
FIG. 1A
, eight unit cells MC are connected in series, thereby forming a memory cell block MCB
0
(or MCB
1
). The memory cell blocks MCB
0
and MCB
1
are connected to a pair of bit lines BL and /BL, respectively.
One end of the memory cell block MCB
0
is connected to the bit line BL via a block selection transistor BST
0
, and the other end is connected to a plate line PL. Similarly, one end of the memory cell block MCB
0
is connected to the bit line /BL via a block selection transistor BST
1
, and the other end is connected to a plate line /PL.
Word lines WL
0
-WL
7
are connected to the respective gates of the cell transistors of each of the memory cell blocks MCB
0
and MCB
1
. Block selection signal lines BS
0
and BS
1
are connected to the gates of the block selection transistors BST
0
and BST
1
, respectively.
As seen from
FIG. 1B
, the plate lines PL and /PL, word lines WL
0
-WL
7
, and block selection signal lines BS
0
and BS
1
extend perpendicular to the cell arrangement of the memory cell blocks MCB
0
and MCB
1
. Accordingly, the memory cell blocks MCB
0
and MCB
1
can commonly use the lines.
As described above, in the series connected TC unit type ferroelectric memory shown in
FIG. 1A
, a plurality of memory cell blocks commonly use the plate lines PL and /PL, word lines WL
0
-WL
7
, block selection signal lines BS
0
and BS
1
, and control circuits for the respective signals. The chip size of the ferroelectric memory can be reduced by increasing the number of memory cell blocks connected to the plate lines PL and /PL, word lines WL
0
-WL
7
and block selection signal lines BS
0
and BS
1
. However, the larger the number of memory cell blocks commonly connected to those lines, the greater the signal delay in the lines.
To solve this problem, a method is employed, in which a branch line is formed of a layer different from that of a trunk line having a large delay or a large amount of current flown therethrough, and is arranged parallel thereto such that the lines are connected to each other at regular intervals.
A description will now be given of a series connected TC unit type ferroelectric memory having such trunk and branch lines as the above.
FIG. 2A
is a circuit diagram illustrating a memory cell array employed in a conventional series connected TC unit type ferroelectric memory.
FIG. 1B
is a sectional view illustrating a memory cell array in which a branch line is formed by a conventional method.
The sectional view schematically illustrates source/drain diffusion layers
101
, gate lines
102
, a plate line
103
, contact plugs
104
, and branch lines
105
for the gate lines
102
. The plate line
103
and branch lines
105
are formed of a single layer. The gate lines
102
correspond to the word lines WL
0
-WL
7
and block selection signal lines BS
0
and BS
1
shown in FIG.
1
A. The sectional structure of each ferroelectric capacitor is not shown.
In the prior art, the branch lines
105
for the gate lines
102
are formed of a line layer provided on the gate line layer
102
, as is shown in FIG.
2
B. In this method, to enable the gate lines
102
to be connected to the branch lines
105
by contact plugs, the pitch (line width+line interval) of the branch lines
105
needs to be made identical to the pitch of the gate lines
102
. In other words, the line width of the branch lines
105
cannot be changed in accordance with a current flowing through the gate lines
102
.
Furthermore, if the line width of the plate line
103
formed of the same layer as the branch lines
105
is increased to avoid problems involving a signal delay in line or electronic migration due to resistors and capacitors, the memory block size is inevitably increased.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the invention, there is provided a semiconductor memory device comprising: a memory cell block which includes series connected memory cells each having a cell transistor having a source and a drain and a ferroelectric capacitor inbetween the source and the drain; a plurality of gate lines connected to gates of the cell transistors of the memory cell block, the gate lines having a predetermined width and being arranged at regular intervals; and a plurality of branch lines formed of a layer different from a layer of the gate lines, arranged parallel to the gate lines, and each connected to a corresponding one of the gate lines, the branch lines having a predetermined width and being arranged at regular intervals, a sum of the predetermined width of the branch lines and an interval between adjacent ones of the branch lines differing from a sum of the predetermined width of the gate lines and an interval between adjacent ones of the gate lines.


REFERENCES:
patent: 5345415 (1994-09-01), Nakao et al.
patent: 5943256 (1999-08-01), Shimizu et al.
patent: 6353550 (2002-03-01), Hirano
patent: 6680499 (2004-01-01), Kumura et al.
patent: 2002-25247 (2002-01-01), None
D. Takashima,

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