Semiconductor memory device including capacitor having stacked s

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257305, 257306, 257307, 257308, H01L 2968, H01L 2978, H01L 2992

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052471969

ABSTRACT:
A dynamic random access memory includes a first conductivity type semiconductor substrate (40), a plurality of word lines (1a, 1b, 1c, 1d), a plurality of bit lines (2a, 2b) and a plurality of memory cells (3). The memory cells (3) are provided at the intersections between the word lines (1a, 1b, 1c, 1d) and the bit lines (2a, 2b). Each of the memory cells (3) includes a pair of impurity regions (6a, 6b) of a second conductivity type, a gate electrode (8) connected to the word line (1a, 1b, 1c, 1d), a storage node (9) and a cell plate (11). A capacitor (5) including the storage node (9) and the cell plate (11) is located above the bit lines (2a, 2b). The storage node (9) is formed to extend from a bottom surface to a side surface of a hole (Ct1, Ct2) formed in an insulator layer (14a, 14b) so as to extend to a surface of one impurity region (6a). The cell plate (11) is formed to interpose the storage node (9) between two layers thereof along the bottom surface and the side surface of the hole (Ct1, Ct2). This enables an increase in capacitance of a capacitor. Combinations of simple manufacture processes facilitate the manufacture of the capacitor of a stacked structure having increased capacitance with respect to mass production.

REFERENCES:
patent: 4899203 (1990-02-01), Ino
patent: 4985718 (1991-01-01), Ishijima
patent: 5005103 (1991-04-01), Know et al.
patent: 5095346 (1992-03-01), Bae et al.
patent: 5177574 (1993-01-01), Yoneda
Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", IEEE IDEM 1988, pp. 592-595.
Kimura et al., "A New Stacked Capacitor DRAM Cell Characterized by a Storage Capacitor on a Bit-Line Structure", IEEE IDEM 1988, pp. 596-599.

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