Semiconductor memory device including an improved data refreshin

Details Semiconductor memory device including an improved data refreshin Semiconductor memory device including an improved data refreshin

1984-10-09

1987-04-21

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Data refresh

365189, 365230, G11C 700, G11C 800

Patent

active

046601805

ABSTRACT:
The dynamic RAM has a refresh circuit with two operation modes. In the first operation mode, a variety of signals necessary for the refresh operation are formed in the dynamic RAM. Accordingly, the refresh operation of the dynamic RAM is performed completely automatically. As long as the refresh operation is being carried out, a busy signal is produced from the dynamic RAM to prevent an erroneous writing operation or reading operation. In the second operation mode, the refresh operation of the dynamic RAM is performed in synchronism with a starting signal supplied from an external unit. The busy signal produced by the dynamic RAM that is working under the first operation mode can be used as a starting signal for the dynamic RAM that is working under the second operation mode. Therefore, the refresh operation is effected in synchronism for the dynamic RAM's that constitute the memory system, and the through-put of the memory system is enhanced.

REFERENCES:
patent: 3811117 (1974-05-01), Anderson, Jr. et al.
patent: 4412313 (1983-10-01), Ackland et al.
patent: 4472792 (1984-09-01), Shimohigashi et al.

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