Semiconductor memory device including additional memory cell blo

Static information storage and retrieval – Read/write circuit – Bad bit

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36523003, 371 491, G11C 700, G11C 2900

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active

053863879

ABSTRACT:
In a semiconductor memory device according to the present invention, the relation between column selection lines and bit line pairs in each memory cell block is defined such that each normal memory cell block and an additional memory cell block share the same column decoder address. Therefore, in a semiconductor memory device having an irregular memory cell array arrangement, it is possible to replace a defective column in any of memory cell blocks by only one type of redundant column.

REFERENCES:
IBM Technical Disclosure Bulletin vol. 28 No. 7 Dec. 1985, pp. 2965-2970.

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