Semiconductor memory device including a write recovery time...

Details Semiconductor memory device including a write recovery time... Semiconductor memory device including a write recovery time...

2007-11-21

2010-02-23

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233120, C365S230030, C365S230080, C365S203000, C365S194000

Reexamination Certificate

active

07668038

ABSTRACT:
A semiconductor memory device may include a clock buffer, a command decoder and a write recovery time control circuit. The clock buffer may generate an internal clock signal based on an external clock signal. The command decoder may generate a write command signal by decoding an external command signal. The write recovery time control circuit may gate a plurality of bank pre-charge control signals in a wave pipeline mode based on the internal clock signal, the write command signal and a write recovery time control signal having a plurality of bits to generate a plurality of gated bank pre-charge control signals. Therefore, the semiconductor memory device may decrease a number of flip-flops required to control a write recovery time.

REFERENCES:
patent: 6185141 (2001-02-01), Hoshita et al.
patent: 6643218 (2003-11-01), Chun
patent: 2008/0123452 (2008-05-01), Kim
patent: 1998-30793 (1998-07-01), None
patent: 10-2003-0009072 (2003-01-01), None

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