Semiconductor memory device including a double-gate dynamic...

Details Semiconductor memory device including a double-gate dynamic... Semiconductor memory device including a double-gate dynamic...

2005-11-22

2005-11-22

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S149000, C365S230060, C257S297000, C257S296000, C257S306000, C257S311000, C257S907000

Reexamination Certificate

active

06967887

ABSTRACT:
A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell (300) includes a storage capacitor (304) and a pass transistor (302). The pass transistor (302) includes a source region (322), drain region (320) and channel region (324). A top gate (318) is disposed over the channel region (324) and a bottom gate (310) is disposed below the channel region (324). The top gate (318) and bottom gate (310) are commonly driven to provide greater control of the pass transistor (302) operation, including an off state with reduced source-to-drain leakage. The DRAM array (400) includes memory cells (414) having pass transistors (500) with double-gate structures. Memory cells (414) within the same row are commonly coupled to a top word line and bottom word line. The resistance of the top and bottom word lines is reduced by a word line strap layer (600). The DRAM array (400) further includes a strapping area that is void of memory cells. Conductive contact between the top word line, bottom word line, and word line strap layer (600) of each row is made within the strapping area by way of strapping vias (604) and top-to-bottom word line vias (602).

REFERENCES:
patent: 6064589 (2000-05-01), Walker
patent: 6207985 (2001-03-01), Walker
patent: 6567330 (2003-05-01), Fujita et al.
patent: 6661699 (2003-12-01), Walker
patent: 6661702 (2003-12-01), Walker
patent: 2003/0035324 (2003-02-01), Fujita et al.
patent: 2004/0208049 (2004-10-01), Walker
U.S. Appl. No. 10/675,042, Walker.
Kuo et al., “A Capacitorless Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications”,IEEE Transactions on Electron Devices, vol. 50, No. 12, Dec. 2003, pp. 2408-2415.

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