Semiconductor memory device in which bit lines connected to...

Details Semiconductor memory device in which bit lines connected to... Semiconductor memory device in which bit lines connected to...

2005-05-24

2005-05-24

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S190000

Reexamination Certificate

active

06898109

ABSTRACT:
In a single intersection type (open bit line type) dynamic RAM, sub-arrays are disposed to the left and right sides of a sense amplifier column placed at the center. Each sub-array has a multiplicity of dynamic memory cells. In the subarrays located to the left and right of the sense amplifier column, bit lines in the same row constitute a complementary bit line pair. In each subarray, shielding wiring patterns that are formed parallel to, and in the same wiring layer of, these bit lines are disposed between the bit lines. All of these wiring patterns are set at a fixed potential, such as a power supply potential. Thus, interference noise between adjacent bit lines is effectively reduced.

REFERENCES:
patent: 5222038 (1993-06-01), Tsuchida et al.
patent: 5272665 (1993-12-01), Uesugi
patent: 5828594 (1998-10-01), Fujii
patent: 5917745 (1999-06-01), Fujii
patent: 59-2365 (1984-01-01), None
patent: 2001-118999 (2001-04-01), None

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