Semiconductor memory device in which a failed memory cell is pla

Details Semiconductor memory device in which a failed memory cell is pla Semiconductor memory device in which a failed memory cell is pla

1995-12-05

1997-11-04

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, G11C 700

Patent

active

056847467

ABSTRACT:
A semiconductor memory device including a memory cell array having memory cells arranged in XY directions, means for storing at least X addresses of failure bit memory cells among memory cells defined by an X address and a Y address in the memory cell array, and address means for generating an address Xe+m (m=positive or negative integer), serving as an internal address, when X address Xe corresponding to the failure bit address is inputted from an external section.

REFERENCES:
patent: 5267205 (1993-11-01), Hamada
"A Flexible Redundancy Technique For High-Density DRAM'S", Masashi Horiguchi, et al. IEEE Journal Of Solid-State Circuits vol. 26, No. 1, pp. 12-17, Jan. 1991.
"A 7-ns 1-Mb BiCMOS ECL SRAM With Shift Redundancy," Atsushi Ohba, et al. IEEE Journal Of Solid-State Circuits vol. 26, No. 4, pp. 507-511, Apr. 1991.

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