Semiconductor memory device improved for externally designating

Static information storage and retrieval – Read/write circuit – Data refresh

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36518904, 36518901, G11C 1300

Patent

active

049891839

ABSTRACT:
In a dynamic random access memory (DRAM), there is provided a refresh decision circuit which detects the external designation of a self refresh mode, in addition to a CAS before RAS refresh mode, by RAS and CAS signals. By detecting a time period of one cycle of the RAS, the self refresh mode is determined. As a result, the timing of change of the RAS signal is less restricted.

REFERENCES:
patent: 3737879 (1973-06-01), Greene et al.
patent: 4636989 (1987-01-01), Ikvzaki
Electronics and Communications in Japan: "A 64Kbit MOS Dynamic RAM with Auto/Self Regresh Functions", by M. Yamada et al., vol. 66-C, No. 1, 1983, pp. 103-110.

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