Semiconductor memory device having write data line

Details Semiconductor memory device having write data line Semiconductor memory device having write data line

2000-11-07

2001-12-11

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S207000, C365S189011, C365S190000

Reexamination Certificate

active

06330202

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a data-rewritable semiconductor memory device.
2. Description of the Background Art
A system LSI has been developed having a DRAM core cell merged with a logic circuit. In order to enhance data transfer rate, simultaneous input/output of several hundred-bit data is possible between the DRAM core cell and the logic circuit. An input terminal for an 1-bit write mask signal is provided per a predetermined number of bits. This write mask signal can be controlled to inhibit data rewriting of corresponding memory cells.
FIG. 6
is a block diagram showing an overall structure of such a DRAM core cell
30
. Referring to
FIG. 6
, DRAM core cell
30
includes a row/column address buffer+clock generation circuit
31
, a row/column decode circuit
32
, a memory mat
33
and a data input/output circuit
34
. In this DRAM core cell
30
, 8k-bit (k is an integer of at least 1) data DQ
1
-DQ
8
k can be input/output simultaneously. An input terminal for 1-bit write mask signal WM is provided per 8-bit data.
Row/column address buffer+clock generation circuit
31
generates row address signals RA
0
-RAm, column address signals CA
0
-CAm, read clock signal CLKR, write clock signal CLKW and the like according to external address signals A
0
-Am (m is an integer of at least 0) and external control signals /RAS, /CAS and /WE to control the whole DRAM core cell
30
.
Memory mat
33
includes a plurality of (three in
FIG. 1
) sense amplifier bands SA
1
-SA
3
and memory arrays MA
1
and MA
2
each provided between the sense amplifier bands. Memory array MA
1
and MA
2
include a plurality of memory cells each for storing 1-bit data. The memory cells are divided into groups each including a predetermined number 8k of memory cells. Each memory cell group is located at a predetermined address determined by a row address and a column address.
Row/column decode circuit
32
designates addresses of memory arrays MA
1
and MA
2
according to row address signals RA
0
-RAm and column address signals CA
0
-CAm supplied from row/column address buffer+clock generation circuit
31
. In sense amplifier bands SA
1
and SA
2
, a sense amplifier+input/output control circuit group described later is provided. The sense amplifier+input/output control circuit group connects 8k memory cells at an address designated by row/column decode circuit
32
to data input/output circuit
34
. Data input/output circuit
34
includes a write driver+read amplifier band
35
and an input/output buffer group
36
. A write driver group and a read amplifier group are provided in write driver+read amplifier band
35
.
The read amplifier group operates synchronously with read clock signal CLKR to supply read data Q
1
-Q
8
k from 8k memory cells to input/output buffer group
36
. Input/output buffer group
36
responds to external control signal /OE to output read data Q
1
-Q
8
k from the read amplfier group to the outside. The write driver group operates synchronously with write clock signal CLKW to write externally supplied write data D
1
-D
8
k into selected 8k memory cells. However, no data is written into memory cells among 8k memory cells that are designated by any write mask signals WM
1
-WMk.
FIG. 7
is a block diagram showing a major part of DRAM core cell
30
in FIG.
6
. For the purpose of simplifying the drawing and description, discussion is presented regarding 8-bit data DQ
1
-DQ
8
and write mask signal WM
1
only.
Referring to
FIG. 7
, memory array MA
1
includes 8 memory blocks
41
.
1
-
41
.
8
, memory array MA
2
includes 8 memory blocks
42
.
1
-
42
.
8
, and 8 sense blocks
43
.
1
-
43
.
8
are provided to sense amplifier bands SA
1
-SA
3
. Although sense blocks
43
.
1
-
43
.
8
are actually dispersed over three sense amplifier bands SA
1
-SA
3
,
FIG. 7
shows the sense blocks collectively placed between memory arrays MA
1
and MA
2
for simplifying the drawing and description.
Referring to
FIG. 8
, memory block
41
.
1
includes a plurality of memory cells MC arranged in a matrix of a plurality of rows and n+1 (n is an integer of at least 1) columns, a plurality of word lines WL provided correspondingly to respective rows, and n+1 pairs of bit lines BL
0
,/BL
0
, . . . BLn, /BLn provided correspondingly to respective n+1 columns. Memory cell MC is a well-known memory cell including an N channel MOS transistor for access and a capacitor for information storage.
When word line WL is set at “H” level which is selection level, memory cell MC at a row corresponding to the word line WL is activated. Then, data can be written/read to/from the memory cell MC. In a write operation, one word line WL is set at the selection H level to activate memory cell MC, and thereafter one of paired bit lines is set at H level while the other bit line is set at “L” level according to write data D. In this way, potential on the bit line is written into desired memory cell MC. In a read operation, potential on paired bit lines BL, /BL is equalized to VBL (=VCC/2), and thereafter one word line WL is set at the selection H level to activate memory cell MC. Accordingly, a slight potential difference according to data stored in memory cell MC is generated between each pair of bit lines BL and /BL. This slight potential difference between bit lines of each pair is amplified to supply voltage VCC and then the potential difference between a pair of bit lines is detected to read data from desired memory cell MC. Other memory blocks
41
.
2
-
41
.
8
and
42
.
1
-
42
.
8
each have the same configuration as that of memory block
41
.
1
. Word lines WL are commonly provided to memory blocks
41
.
1
-
41
.
8
and
42
.
1
-
42
.
8
.
Row decoders
44
and
45
are provided correspondingly to respective memory arrays MA
1
and MA
2
. Row decoders
44
and
45
select any of word lines WL included in respective memory arrays MA
1
and MA
2
according to row address signals RA
0
-RAm to set the selected word line WL at the selection H level.
A row/column decoder
46
is provided correspondingly to sense blocks
43
.
1
-
43
.
8
. Further, correspondingly to sense blocks
43
.
1
-
43
.
8
respectively, read data lines MIOR
1
, /MIOR
1
, . . . MIOR
8
, /MIOR
8
, write data lines MIOW
1
, /MIOW
1
, . . . MIOW
8
, /MIOW
8
, and write driver+read amplifier+input/output buffers
47
.
1
-
47
.
8
are provided. Row decoders
44
and
45
and row/column decoder
46
are included in row/column decode circuit
32
and write driver+read amplifier+input/output buffers
47
.
1
—
47
.
8
are included in data input/output circuit
34
.
Row/column decoder
46
generates various internal signals SHRL, SHRR, BLEQ, VBL, SE, /SE, CSLR
0
-CSLRn, CSLW
0
-CSLWn, and WM
1
according to row address signals RA
0
-RAm, column address signals CA
0
-CAm and write mask signal WM
1
to control sense blocks
43
.
1
-
43
.
8
.
Sense blocks
43
.
1
-
43
.
8
are coupled to memory blocks
41
.
1
-
41
.
8
when signal SHRL is set at “H” level which is activation level, and coupled to memory blocks
42
.
1
-
42
.
8
when signal SHRR is set at the activation H level. Sense blocks
43
.
1
-
43
.
8
equalize, to bit line potential VBL, potential on each pair of bit lines BL and /BL of memory blocks
41
.
1
-
41
.
8
and
42
.
1
-
42
.
8
when signal BLEQ is at the activation H level.
In response to signals SE and /SE set at the activation H level and “L” level respectively, sense blocks
43
.
1
-
43
.
8
amplify a slight potential difference generated between paired bit lines BL and /BL to supply voltage VCC. Further, sense blocks
43
.
1
-
43
.
8
each select one pair of bit lines from n+1 pairs of bit lines BL
0
, /BL
0
, . . . BLn, /BLn included in a connected memory block according to signals CSLR
0
-CSLRn to connect the selected bit line pair to a corresponding pair of read data lines MIOR and /MIOR.
Sense blocks
43
.
1
-
43
.
8
are each activated when write mask signal W

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