Semiconductor memory device having word line and bit line test c

Details Semiconductor memory device having word line and bit line test c Semiconductor memory device having word line and bit line test c

1991-10-10

1994-07-19

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Testing

365200, 36523006, H01L 2100, G11C 2900

Patent

active

053315944

ABSTRACT:
A semiconductor memory device such as a ROM is provided with a word line test circuit and a word line drive circuit. The word line test circuit outputs a high level signal when a test signal is applied and a low level signal when the test signal is not applied. The word line drive circuit drives the respective word lines in the memory cell array, and is connected to the output of the word line test circuit, so that when driving one group of word lines (either the odd-numbered word lines or the even-numbered word lines), a high level signal is applied to the one group of word lines, and when not driving the one group of word lines, a low level signal is applied to the one group of word lines. On the other hand, when driving the other group of word lines, a high level signal is applied to the other group of word lines, and when not driving the other group of word lines, the output signal from the word line test circuit is applied to the other group of word lines, thereby enabling short circuits between adjacent word lines to be identified quickly. A bit line test switch circuit is provided which is connected to the bit lines in the memory cell array. In response to a test signal, the bit line test switch circuit applies signals of different levels to the odd-numbered and even-numbered bit lines respectively, and short circuits between adjacent bit lines can be identified quickly.

REFERENCES:
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patent: 4464750 (1984-08-01), Tatematsu
patent: 4685086 (1987-08-01), Tran
patent: 4779272 (1988-10-01), Kohda et al.
patent: 4896322 (1990-01-01), Kraus et al.
patent: 4920515 (1990-04-01), Obata
patent: 4956819 (1990-09-01), Hoffmann et al.
Patent Abstracts of Japan vol. 14, No. 581, (P-1147) Dec. 26, 1990. The corresponding Japanese Patent Publication No. 2-249196 is also enclosed herewith.

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