Semiconductor memory device having well region

Details Semiconductor memory device having well region Semiconductor memory device having well region

1996-04-25

1997-09-16

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

365181, Q11C 1300

Patent

active

056687559

ABSTRACT:
A semiconductor memory device is obtained having a triple well structure improved by preventing latch up or the like. In this semiconductor memory device, a substrate potential is applied to a p type well region in a memory cell region through a p.sup.+ type impurity region and a ground potential is applied to a p type well region in a peripheral circuit region through the P.sup.+ type impurity region. By this structure, the peripheral circuit region including a complementary type field effect transistor having the possibility of generation of latch up is kept at a stable potential even at the time of power-on. Further, since the substrate potential generated by internal circuitry is applied to a first well region of the memory cell region, reliable operation of the memory cell region is maintained.

REFERENCES:
patent: 5055897 (1991-10-01), Canepa
patent: 5281842 (1994-01-01), Yasuda et al.
1989 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 248-249.

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