Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-04-25
2006-04-25
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S200000, C365S201000
Reexamination Certificate
active
07036056
ABSTRACT:
In a read out mode, a NAND circuit to which latch data of both bit lines are input provides an L output when potentials of the bit line pair are constantly identical, and provides an H output when the potentials of the bit line pair change, even when the word line rendered active is switched. In a writing mode, the NAND circuit provides an L output. In a reading mode, H is applied to the gate of a first transistor that connects a bit line BL with the NAND circuit. In a writing mode, H is applied to the gate of the first transistor or a second transistor that connects a bit line /BL with the NAND circuit. Potential change occurs at the bit line pair according to an output of the NAND circuit.
REFERENCES:
patent: 4879689 (1989-11-01), Atsumi et al.
patent: 5339273 (1994-08-01), Taguchi
patent: 5495448 (1996-02-01), Sachdev
patent: 6038180 (2000-03-01), Hoshi
patent: 7-287981 (1995-10-01), None
De'cady Albert
McDermott Will & Emery LLP
Nguyen Steve
Renesas Technology Corp.
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