Semiconductor memory device having thin film transistor and meth

Details Semiconductor memory device having thin film transistor and meth Semiconductor memory device having thin film transistor and meth

1995-01-17

1996-05-28

Clawson, Jr., Joseph E.

Static information storage and retrieval

Systems using particular element

Capacitors

365154, 365156, 257307, 257308, 257310, 257311, G11C 11412

Patent

active

055218598

ABSTRACT:
A thin film transistor (TFT) load type static random access memory (SRAM) which includes a memory capacitor in addition to the stray capacitance. The SRAM includes a semiconductor substrate and a memory cell provided on the semiconductor substrate. The memory cell includes first and second transfer transistors, first and second driver transistors, first and second thin film transistor loads and first and second memory capacitors. The first and second memory capacitors include a storage electrode, a dielectric layer which covers the storage electrode, and an opposing electrode formed on the dielectric layer. A connection region is provided in which the storage electrode of the first memory capacitor, the drain region of the second thin film transistor load and the gate electrode of the first driver transistor are connected.

REFERENCES:
patent: 4764801 (1988-08-01), McLaughlin et al.
patent: 4805147 (1989-02-01), Yamanaka et al.
patent: 4833644 (1989-05-01), Plus et al.
patent: 4849801 (1989-07-01), Honjyo et al.
patent: 4853894 (1989-08-01), Yamanaka et al.
patent: 4984200 (1991-01-01), Saitoo et al.
patent: 5051951 (1991-09-01), Maly et al.
patent: 5111427 (1992-05-01), Kobayashi et al.
patent: 5204834 (1993-04-01), Ochii et al.
patent: 5214296 (1993-05-01), Nakata et al.
patent: 5214304 (1993-05-01), Ema et al.
patent: 5239196 (1993-08-01), Ikeda et al.
Yamanaka et al., "A 25 .mu.m.sup.2 New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity," International Electron Devices Meeting, Dec. 1988, San Francisco, CA, pp. 48-51.
Ishibashi et al., "An .alpha.-Immune, 2-V Supply Voltage SRAM Using a Polysilicon PMOS Load Cell," IEEE Journal of Solid-State Circuits, vol. 25, No. 1, Feb. 1990, New York, NY, pp. 55-60.
Adan et al., "A Half-Micron SRAM Cell Using a Double-Gated Self-Aligned Polysilicon PMOS Thin Film Transistor (TFT) Load," Symposium on VLSI Technology, Jun. 1990, Honolulu, Japan, pp. 19-20.
Yamanaka, et al., "A 25 .mu.m.sup.2 New Poly-Si PMOS Load (PPL) SRAM Having Excellent Soft Error Immunity", International Electron Devices Meeting, Dec. 1988, pp. 48-51.
Ishibashi, et al., "A .alpha.-Immune, 2-V Supply Voltage SRAM Using a Polysilicon PMOS Load Cell", IEEE Journal of Solid-State Circuits, vol. 25, No. 1, Feb. 1990, pp. 55-60.
Adan, et al., "A Half-Micron SRAM Cell Using a Double-Gated Self-Aligned Polysilicon PMOS Thin Film Transistor (TFT) Load", Symposium on VLSI Technology, Jun. 1990, pp. 19-20.

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