Semiconductor memory device having testing function and testing

Details Semiconductor memory device having testing function and testing Semiconductor memory device having testing function and testing

1990-01-24

1991-06-11

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

36518907, 365233, G11C 2900

Patent

active

050238400

ABSTRACT:
A semiconductor memory device comprises a high voltage detection circuit (20). A sense amplifier driving signal generating circuit (92) delays a word line driving signal (R) and outputs the delayed word line driving signal (R) as a sense amplifier driving signal (.phi.s). An X decoder (300) applies the word line driving signal (R) to any of word lines (WL). A sense amplifier (510) amplifies potential difference between a bit line pair (BL, BL) in response to the sense amplifier driving signal (.phi.s). The high voltage detection circuit (20) generates a test signal (T) when high voltage is applied to an input terminal (81) during a test. A delay time of the sense amplifier driving signal generating circuit (92) is reduced in response to the test singal (T).

REFERENCES:
patent: 4571503 (1986-02-01), Tobita
patent: 4819212 (1989-04-01), Nakai et al.
patent: 4841233 (1989-06-01), Yoshida
"Contrivance and Development of Sense Amplifier Which is the Key to the of a Large Capacity MOS RAM" [sic], Nikkei Electronics publication dated Jan. 8, 1989, pp. 110-133.
Hugh McAdams et al., "A 1-Mbit CMOS Dynamic RAM with Design-For Test Functions," IEEE Journal of Solid State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 635-642.

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