Semiconductor memory device having test mode for data access...

Details Semiconductor memory device having test mode for data access... Semiconductor memory device having test mode for data access...

2004-12-28

2010-10-19

Kim, Matt (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C365S201000, C711SE12001

Reexamination Certificate

active

07818526

ABSTRACT:
A semiconductor memory device for measuring a data access time by controlling data output operation, including: a pipe latch control unit for generating an input control signal based on a test mode signal; a pipe latch unit for receiving data and controlling the data according to a CAS latency in synchronization with a clock signal at a normal mode or passing the data without synchronization with the clock signal at a test mode based on the input control signal; an output control unit for generating an output node control signal based on the test mode signal; and an output unit for controlling an output data outputted from the pipe latch means according to the CAS latency in synchronization with the clock signal at the normal mode or passing the output data without synchronization with the clock signal at the test mode based on the output node control signal.

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