Static information storage and retrieval – Read/write circuit – Testing
Patent
1993-07-09
1994-11-15
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Testing
36518903, 365194, 365195, G11C 700
Patent
active
053654811
ABSTRACT:
A semiconductor memory device according to the present invention includes a memory cell array, internal circuits for reading and writing of data of the memory cell array, a test mode controller, and power-on-reset circuits. The test mode controller sets a test mode of the memory cell array in response to a predetermined pattern of change of logic levels of at least several control signals out of a plurality of control signals for controlling the internal circuits. The power-on-reset circuits set the test mode controller in an initial state over a variable period which is defined based on a timing of change of a logic level of a control signal determining a timing of setting of the test mode out of the at least several control signals, in response to power-on. As a result, it is possible to prevent the semiconductor memory device from erroneously entering the test mode caused by a noise or the like after power-on.
REFERENCES:
patent: 5134586 (1992-07-01), Steele
patent: 5134587 (1992-07-01), Steele
patent: 5204837 (1993-04-01), Suwa et al.
patent: 5270977 (1993-12-01), Iwamoto et al.
Glembocki Christopher R.
LaRoche Eugene R.
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Semiconductor memory device having test mode and method of setti does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device having test mode and method of setti, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having test mode and method of setti will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1103139