Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-04-20
2001-09-11
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S063000, C365S051000
Reexamination Certificate
active
06288957
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and method for testing a semiconductor therewith, and more particularly to a semiconductor memory device having a test mode and a method for testing a semiconductor therewith.
2. Description of the Background Art
In recent years, integration of a DRAM has been quadrupled every new generation. The higher integration in DRAM means longer test time. Hence, various techniques for reducing test cost by shortening the test time has been proposed.
One technique for reducing the test cost is a so-called burn-in test. In the burn-in test, a number of DRAMs are placed on a single test board and driven under the conditions of high temperature and high power supply voltage to accelerate the occurrence of initial failure. With this technique, the test cost of one DRAM can be reduced because a number of DRAMs are tested together.
Conventionally, however, as a new test board has to be manufactured along with the progress in DRAM generation, the test cost tends to increase. In addition, lately other tests are also required to be performed during the burn-in test, and a test-facilitating design (such as test mode) has been proposed to meet the need.
Further, in order to reduce chip area, shrinkage of layout area of test-related circuitry is needed as well as of other peripheral circuitry.
SUMMARY OF THE INVENTION
Therefore, one object of the present invention is to provide a semiconductor memory device and a method for testing a semiconductor allowing reduction in test cost.
Further, another object of the present invention is to provide a semiconductor memory device with a small chip area.
According to one aspect of the present invention, a plurality of signal generation circuits are provided corresponding to a plurality of test circuits dispersedly formed on a semiconductor substrate. Each signal generation circuit is placed in the proximity of the corresponding test circuit. Thus, a signal transmission line for a test signal can be reduced to shrink the chip area, compared with the conventional case where a test signal is supplied to each test circuit from the signal generation circuit arranged in the center of the semiconductor substrate.
According to another aspect of the present invention, a semiconductor memory device which can be selectively set to one of a plurality of specs includes a signal generation circuit supplying a test mode entry signal as an output in response to supply of a higher voltage than a power supply voltage to N (1≦N≦M−1) signal input terminals predetermined according to the set spec among first to Mth signal input terminals. As a combination of signal input terminals receiving a high voltage for test mode entry is different from chip to chip according to its spec, chips with different specs can be readily distinguished. Thus, an occurrence of trouble during the test process can be prevented and the reduction in test cost can be achieved.
According to still another aspect of the present invention, in a case where a semiconductor memory device receiving first to Mth address signals and a semiconductor memory device receiving first to Nth (N>M) address signals are manufactured according to same process rule, the semiconductor memory device receiving first to Nth address signals is provided with a signal generation circuit provided corresponding to each test mode and supplying a test signal in response to an input of an m (1≦m≦M) address signals predetermined according to the corresponding test mode among first to Mth address signals. Thus, the same signal generation circuit can be shared between the semiconductor memory device receiving first to Mth address signals and the semiconductor memory device receiving first to Nth address signals, resulting in more efficient design. In addition, as the number of lines used for address signals can be reduced compared with a case where a test signal is generated based on first to Nth address signals, reduction in chip area can be achieved.
According to a still further aspect of the present invention, a signal generation circuit selectively generating a signal of a first or a second logical level during test mode and a switching circuit supplying the signal of the first or the second logical level generated by the signal generation circuit instead of a most significant bit address signal of a plurality of address signals to a select circuit at the time of test mode are provided. Thus, even when the semiconductor memory device is placed on a test board without a line for the most significant bit address signal, a desired test can be performed through the generation of the signal of first or second logical level in the semiconductor memory device. Therefore, the existing test board can be employed and the test cost can be reduced.
According to a still further aspect of the present invention, a switching circuit supplying a first clock signal generated by a clock generation circuit to a refresh counter during test mode and supplying a second clock signal generated by a variable frequency-dividing circuit to the refresh counter during other time period is provided. Hence, a self refresh can be performed even when a frequency-dividing ratio of the variable frequency-dividing circuit has not been set. Then, a number of semiconductor memory devices can be arranged like a matrix on a single test board, data can be written to all semiconductor memory devices simultaneously and a test to read data from semiconductor memory devices row by row can be easily performed. Hence, an existing test board can be utilized and the test cost can be reduced.
According to a still further aspect of the present invention, a counter with a count value incremented in response to designation of auto refresh operation designating one word line among a plurality of word lines according to the count value, and a control circuit suspending the increment of the counter during test mode are provided. Thus, as one word line can be selected once with the input of auto refresh command, a disturb test can be performed more rapidly compared with a conventional case where three command inputs, that is, active, write (read) and precharge, are required for a selection of one word line. The present invention is particularly effective when a number of semiconductor memory devices are placed on one test board for test where heavy load is applied on a tester and command input cannot be performed rapidly. Thus, an existing test board can be utilized and the reduction in test cost can be achieved.
According to a still further aspect of the present invention, provided is a control circuit prohibiting inputs of control signals other than a control signal of a first logical level when a predetermined control signal among a plurality of control signals is set to the first logical level, and permitting inputs of the plurality of control signals when the predetermined control signal is set to a second logical level during the self refresh operation. Thus, when an excessive current is consumed at the simultaneous test of a number of semiconductor memory devices placed on a single test board, a desired test can be performed for a part of the semiconductor memory devices while self refresh is performed for the rest of the semiconductor memory devices. Hence, an existing test board can be utilized and the reduction in test cost can be achieved.
According to a still further aspect of the present invention, when a number of semiconductor memory devices are placed on a single test board and tested, each semiconductor memory device is provided with a control circuit prohibiting inputs of control signals other than a control signal of a first logical level when a predetermined control signal among a plurality of control signals is set to the first logical level, and permitting input of the plurality of control signals when the predetermined control signal is set to a second logical level during the self refresh operation. Then, a predetermined number of sem
Furutani Kiyohiro
Katoh Tetsuo
Yamashita Mitsutomi
Le Vu A.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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