Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-10-22
2004-10-26
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S233100
Reexamination Certificate
active
06809975
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a memory system using the same, and more particularly to a semiconductor memory device taking in a plurality of external signals synchronization with a clock signal and a memory system using the same.
2. Description of the Background Art
A semiconductor memory device such as a DRAM, an SDRAM (Synchronous DRAM) or a DDR (Double Date Rate) DRAM conventionally has a test mode for improving the efficiency of a product test performed by a vender and facilitating the product test.
FIG. 43
is a block diagram showing the important sections of such a DDR SDRAM. In
FIG. 43
, DDR SDRAM includes a test mode entry circuit
301
and a decoding circuit
302
. A test mode entry set command TMES and a high voltage SVIH (Super VIH) sufficiently higher than an external power supply voltage VCC are applied to predetermined external pins (e.g., bank select BA1 pins), test mode entry circuit
301
sets test mode entry signal TMODE at active level of “H” level.
In response to the setting of test mode entry signal TMODE at “H” level, decoding circuit
302
is activated and a test mode register set command TMRS is applied thereto. In addition, in response to the application of test mode set data TMSD (address signals A
0
to A
6
), decoding circuit
302
selects one test mode signal (e.g., TMx) from among (x+1) (where x is an integer not smaller than 0) test mode signals TM
0
to TMx based on test mode set data TMSD and sets selected signal TMx at active level of “H” level. As a result, SDRAM is set in a test mode corresponding to test mode signal TMx which is set at “H” level.
The reason for allowing DDR SDRAM to enter the test mode using high voltage SVIH sufficiently higher than external power supply voltage VCC is to prevent DDR SDRAM from entering the test mode by an ordinary user.
The test mode entry method using high voltage SVIH has, however, the following disadvantage. While a single device can enter a test mode, a module such as a registered DIMM (Dual In Memory Module) into which a plurality of devices are incorporated cannot enter a test mode.
That is, as shown in
FIG. 44
, registered DIMM includes one register
303
and a plurality of DDR SDRAM
304
. An external control signal CNT and an external address signal ADD are inputted into a plurality of DDR SDRAM
304
in parallel through register
303
. Due to this, even if high voltage SVIH is applied to an external pin for a bank select signal BA
0
which is included in address signal ADD, the presence of register
303
prevents high voltage SVIH from being applied to SDRAM
304
, with the result that registered DIMM cannot enter a test mode.
SUMMARY OF THE INVENTION
It is, therefore, a main object of the present invention to provide a semiconductor memory device capable of entering a test mode even if an external signal is inputted thereinto through a register, and a memory system using the same.
A semiconductor memory device according to the present invention includes a decoder which outputs one command signal among a plurality of command signals based on a combination of the logic levels of a plurality of external signals taken in, and a first signal generation circuit which outputs a test mode entry signal for enabling the semiconductor memory device to enter a test mode in accordance with the output of the plurality of command signals from the decoder in a predetermined order. This enables the semiconductor memory device to enter the test mode without using a high voltage. Therefore, the semiconductor memory device can enter the test mode even if the external signals are applied through a register. Further, since the semiconductor memory device enters the test mode only if the plurality of command signals are inputted in a predetermined order, the probability that the semiconductor memory device enters the test mode while an ordinary user is using the semiconductor memory device is low.
In addition, a memory system according to the present invention includes a plurality of the above-described semiconductor memory devices. Signals other than external data signals among the plurality of external signals are applied to the plurality of semiconductor memory devices in common and the external data signals are individually applied to the respective semiconductor memory devices. In this case, it is possible to make the operation timings of the plurality of semiconductor memory devices consistent with one another.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5121007 (1992-06-01), Aizaki
patent: 6400625 (2002-06-01), Arimoto et al.
patent: 6614713 (2003-09-01), Tanizaki et al.
patent: 6615391 (2003-09-01), Brown et al.
patent: 11-312398 (1999-11-01), None
Kuge Shigehiro
Yamaoka Shigeru
Renesas Technology Corp.
Tran M.
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