Semiconductor memory device having test mode

Details Semiconductor memory device having test mode Semiconductor memory device having test mode

1998-07-08

2001-02-13

Nguyen, Hoa T. (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S743000

Reexamination Certificate

active

06189119

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, particularly to a semiconductor memory device having a test mode.
2. Description of the Background Art
As the storage capacity of a semiconductor memory device (SRAM, DRAM, etc.) increases, an increasing number of address signal input terminals and data signal input/output terminals
34
are provided to the semiconductor memory device.
FIG. 8
is a block diagram showing an entire structure of an SRAM provided with a number of such address signal input terminals and data signal input/output terminals. Referring to
FIG. 8
, the SRAM includes groups of address signal input terminals
31
-
33
, a group of data signal input/output terminals
34
, and control signal input terminals
35
-
38
.
Address signals A
0
-An (n is an integer of 0 or more) are externally input to groups of address signal input terminals
31
-
33
. Address signals (e.g. A
4
-A
8
, A
12
-An) for designating a row among address signals A
0
-An are input to group of address signal input terminals
31
. Address signals (e.g. A
0
, A
2
, A
3
, A
10
) for designating a column among address signals A
0
-An are supplied to group of address signal input terminals
32
. Address signals (e.g. A
1
, A
9
, A
11
) for designating a block among address signals A
0
-An are input to group of address signal input terminals
33
. Group of data signal input/output terminals
34
is used for input/output of data signals D
0
-Dm (m is an integer of 0 or more). Write control signal /W, chip select signals /S
1
and S
2
and output enable signal /OE are supplied to control signal input terminals
35
-
38
respectively.
The SRAM further includes a row input buffer
41
, a column input buffer
42
, a block input buffer
43
, a row decoder
44
, a column decoder
45
, a block decoder
46
, a memory array
47
, a clock generator
48
, a sense amplifier
49
, an output buffer
50
, an input data control circuit
51
, and gate circuits
52
-
54
.
Row input buffer
41
generates amplification signals and inversion-amplification signals of address signals A
4
-A
8
and A
12
-An supplied externally via address signal input terminal group
31
, and supplies the generated signals to row decoder
44
and clock generator
48
.
Column input buffer
42
generates amplification signals and inversion-amplification signals of address signals A
0
, A
2
, A
3
and A
10
input from address signal input terminal group
32
, and supplies the generated signals to column decoder
45
and clock generator
48
.
Block input buffer
43
generates amplification signals and inversion-amplification signals of address signals A
1
, A
9
and A
11
supplied externally via address signal input terminal group
33
, and supplies the generated signals to block decoder
46
and clock generator
48
.
Memory array
47
is divided into a plurality of memory blocks. Each memory block includes a plurality of memory cells each storing data of 1 bit. The memory cells are grouped in advance such that each group includes m+1 cells. The number of memory cells in each group m+1 is equal to the number of data signal input/output terminals. Each memory cell group is arranged at a prescribed address determined by a row address, a column address and a block address.
Row decoder
44
designates a row address in memory array
47
according to the amplification signals and inversion-amplification signals of address signals A
4
-A
8
and A
12
-An supplied from row input buffer
41
. Column decoder
45
designates a column address in memory array
47
according to the amplification signals and inversion-amplification signals of address signals A
0
, A
2
, A
3
and A
10
supplied from column input buffer
42
. Block decoder
46
designates a block address in memory array
47
according to the amplification signals and inversion-amplification signals of address signals Al, All and A
9
supplied from block input buffer
43
.
Clock generator
48
and gate circuits
52
-
54
select a prescribed operation mode according to signals /W, /S
1
, S
2
, and /OE supplied externally via control signal input terminals
35
-
38
as well as the amplification signals and inversion-amplification signals of address signals A
0
-An supplied from input buffers
41
-
43
, and controls the entire SRAM.
In a reading mode, sense amplifier
49
reads data signals D
0
-Dm from a memory cell group located at an address designated by decoders
44
-
46
. Output buffer
50
outputs data signals D
0
-Dm read by sense amplifier
49
externally via data signal input/output terminal group
34
in the read mode. In a write mode, input data control circuit
51
writes data signals D
0
-Dm supplied externally via data signal input/output terminal group
34
into a memory cell group located at an address designated by decoders
44
-
46
.
An operation of the SRAM shown in
FIG. 8
is hereinafter described briefly. In a writing operation, signals /W and /S
1
are at “L” level, signals S
2
and /OE are at “H” level, address signals A
0
-An are supplied to groups of address signal input terminals
31
-
33
, and write data signals D
0
-Dm are supplied to data signal input/output terminal group
34
. Decoders
44
-
46
designate any memory cell group in memory array
47
according to address signals A
0
-An. Externally supplied data signals D
0
-Dm are written by input data control circuit
51
into the memory cell group designated by decoders
44
-
46
.
In a reading operation, signals /OE and /S
1
are at “L” level, signals S
2
and /W are at “H” level, and address signals A
0
-An are supplied to groups of address signal input terminals
31
-
33
. Decoders
44
-
46
designate any memory cell group in memory array
47
according to address signals A
0
-An. Sense amplifier
49
reads data D
0
-Dm in the memory cell group designated by decoders
44
-
46
. Data D
0
-Dm read by sense amplifier
49
are output to data signal input/output terminal group
34
by output buffer
50
.
A burn-in test for acceleratedly causing any initial failure is applied to such an SRAM prior to delivery, in order to eliminate early failures caused after delivery. The burn-in test is conducted by placing a number of SRAMs on a single test board, supplying address signals A
0
-An and data signals D
0
-Dm in parallel to the group of SRAMs, and driving the SRAMs under extreme conditions (high temperature, high supply voltage etc.) severer than normal conditions.
If a conventional package such as the SOP (Small Outline Package) or TSOP (Thin Small Outline Package) is used for an SRAM, external pins
62
are arranged around only the periphery of a package
61
as shown in FIG.
9
. In this case, interconnection lines
63
on the test board can be constituted of a single-layer interconnection.
However, if a modern small package such as the CSP (Chip Scale Package) is used for an SRAM, external pins
72
are arranged in rows and columns at the bottom surface of a package
71
as shown in FIG.
10
. If interconnection lines
73
on the test board is constituted of the single-layer interconnection, interconnection lines
73
cannot be connected to external pins
72
located at the central portion even if interconnection lines
73
can be connected to external pins
72
arranged around the periphery of the bottom surface of the package
71
. Although interconnection lines
73
on the test board can be constituted of a multi-layer interconnection to allow all of the external pins
72
to be connected to interconnection lines
73
, the higher cost of the test board leads to increase in the cost of testing.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device by which the cost of testing can be decreased.
A first semiconductor memory device according to the present invention is briefly described as the one provided with a counter counting the number of pulses (pulse number) of an external clock signal and designating each of a plurality of addresses according to a value of the counted number in a te

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