Semiconductor memory device having test mode

Details Semiconductor memory device having test mode Semiconductor memory device having test mode

2000-04-24

2001-03-13

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S189110

Reexamination Certificate

active

06201748

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a semiconductor memory device outputting a test mode signature in a test mode.
2. Description of the Prior Art
FIG. 15
is a block diagram showing the structure of a conventional dynamic random access memory (hereinafter referred to as “DRAM”). Referring to
FIG. 15
, this DRAM comprises a clock generation circuit
101
, a row and column address buffer
102
, a row decoder
103
, a column decoder
104
, a memory mat
105
, an input buffer
108
and an output buffer
109
, and the memory mat
105
includes a memory array
106
and a sense amplifier+ input/output control circuit
107
.
The clock generation circuit
101
selects a prescribed operation mode on the basis of externally supplied control signals ext.ZRAS, ext.ZCAS and ext.ZWE and controls the overall DRAM.
The row and column address buffer
102
generates row address signals RA
0
to RAm and column address signals CA
0
to CAm on the basis of externally supplied address signals ext.A
0
to ext.Am (m:integer of at least 0) and supplies the generated row address signals RA
0
to RAm and column address signals CA
0
to CAm to the row decoder
103
and the column decoder
104
respectively.
The memory array
106
includes a plurality of memory cells each storing 1-bit data. The plurality of memory cells are previously divided into groups each including n (n: integer of at least 1) memory cells. Each memory cell group is arranged on a prescribed address decided by a row address and a column address.
The row decoder
103
specifies a row address of the memory array
106
in response to the row address signals RA
0
to RAm supplied from the row and column address buffer
102
. The column decoder
104
specifies a column address of the memory array
106
in response to the column address signals CA
0
to CAm supplied from the row and column address buffer
102
.
The sense amplifier+input/output control circuit
107
connects the n memory cells of the address specified by the row decoder
103
and the column decoder
104
to an end of a data bus DB. Another end of the data bus DB is connected to the input buffer
108
and the output buffer
109
. The input buffer
108
supplies externally input data D
1
to Dn to the selected n memory cells through the data bus DB in response to the control signal ext.ZWE in a write mode. The output buffer
109
outputs read data D
1
to Dn from the selected n memory cells in response to an externally input control signal ZOE in a read mode.
In the read mode, the external address signals ext.A
0
to ext.Am are supplied while the external control signal ext.ZRAS is set low for activation and thereafter the external control signal ext.ZCAS is set low for activation. Thus, the row decoder
103
and the column decoder
104
select n memory cells so that read data from the n memory cells are output through the sense amplifier+input/output control circuit
107
and the output buffer
109
.
In the write mode, the external data D
1
to Dn and the external address signals ext.A
0
to ext.Am are supplied while the external control signal ext.ZRAS is set low for activation and thereafter the external control signals ext.ZCAS and ext.ZWE are set low for activation. Thus, the row decoder
103
and the column decoder
104
select n memory cells so that the data D
1
to Dn are written in the selected n memory cells through the input buffer
108
and the sense amplifier+input/output control circuit
107
.
Such a DRAM stores a test circuit for testing whether or not the DRAM is normal before shipping, and various test modes can be set through input timing for the external control signals ext.ZRAS, ext.ZCAS and ext.ZWE and combination of the external address signals ext.A
0
to ext.Am.
No problem arises if the DRAM is regularly set in a desired test mode in testing. If the DRAM is set in a test mode different from the desired one or not set in a test mode, however, no desired test is made but a defective unit may be shipped.
When setting a test mode of forcibly supplying an internal power supply voltage of the DRAM from outside, for example, the internal power supply voltage cannot be externally monitored and it is impossible to determine whether or not the internal power supply voltage is at the externally supplied level. Therefore, a desired test may not be performed but a defective unit may be shipped.
If the DRAM outputs a test mode signature responsive to the test mode only when set in the test mode, however, it is possible to determine whether or not the test mode is set by monitoring the test mode signature. Therefore, the DRAM stores a circuit for generating a test mode signature responsive to a test mode and outputting the same. A part of the DRAM related to test mode signatures is now described in detail.
FIG. 16
is a block diagram showing the structure of a part of the conventional DRAM related to test mode setting. Referring to
FIG. 16
, this DRAM includes input circuits
111
to
113
, a WCBR determination circuit
114
, a super VIH determination circuit
115
and an address determination circuit
116
.
The input circuits
111
to
113
transmit the external control signals ext.ZRAS, ext.ZCAS and ext.ZWE and the external address signals ext.A
1
to ext.A
3
to the DRAM. The WCBR determination circuit
114
sets an internal control signal WCBR high for activation when the external control signals ext.ZCAS and ext.ZWE fall low in advance of the external control signal ext.ZRAS.
The super VIH determination circuit
115
is activated responsively when the signal WCBR goes high for activation, and sets a signal &phgr;SVIH high for activation responsively when a super VIH level SVIH sufficiently higher than a power supply voltage VCC is supplied to an input terminal for the external address signal ext.A
1
.
The address determination circuit
116
is activated responsively when the signal &phgr;SVIH goes high for activation for setting any of test signals TM
1
to TM
4
high for activation in response to the combination (00 to 11) of the levels of the external address signals ext.A
2
and ext.A
3
, and reset by a reset signal RES.
As shown in
FIG. 17
, the address determination circuit
116
includes inverters
121
to
125
, AND gates
126
and
127
, clocked inverters
128
and
129
and NOR gates
130
and
131
. The external address signal ext.A
2
is input in first input nodes of the AND gates
126
and
127
through an input circuit
113
a
. The external address signal ext.A
3
is input in a second input node of the AND gate
126
through an input circuit
113
b
and input in a second input node of the AND gate
127
through the input circuit
113
b
and the inverter
121
.
Output signals &phgr;
126
and &phgr;
127
from the AND gates
126
and
127
are input in first input nodes of the NOR gates
130
and
131
through the clocked inverters
128
and
129
respectively. The signal &phgr;SVIH is input in the gates of N-channel MOS transistors of the clocked inverters
128
and
129
, and input in the gates of P-channel MOS transistors of the clocked inverters
128
and
129
through the inverters
122
and
123
. The reset signal RES is input in second input nodes of the NOR gates
130
and
131
. The inverters
124
and
125
are connected between output nodes and the first input nodes of the NOR gates
130
and
131
respectively. The NOR gates
130
and
131
output the signals TM
1
and TM
2
.
When the signals ext.A
2
and ext.A
3
are both high, i.e., when the combination is “11”, the output signals &phgr;
126
and &phgr;
127
of the AND gates
126
and
127
go high and low respectively. When the signals ext.A
2
and ext.A
3
are high and low respectively, i.e., when the combination is “10”, the output signals &phgr;
126
and &phgr;
127
of the AND gates
126
and
127
go low and high respectively. When the signal &phgr;SVIH goes high for activation, the clocked inverters
128
and
129
are activated so that the si

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